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1. 发明授权

US06232646B1 Shallow trench isolation filled with thermal oxide 失效
标题翻译：浅沟隔离填充热氧化物
公开(公告)号：US06232646B1
公开(公告)日：2001-05-15
申请号：US09082607
申请日：1998-05-20
申请人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
发明人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
IPC分类号： H01L2900
CPC分类号： H01L21/7621 , H01L21/76232
摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.
摘要翻译：一种用于产生浅沟槽隔离的半导体装置和方法。该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域。随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

2. 发明授权

US06444539B1 Method for producing a shallow trench isolation filled with thermal oxide 有权
标题翻译：用于生产填充有热氧化物的浅沟槽隔离体的方法
公开(公告)号：US06444539B1
公开(公告)日：2002-09-03
申请号：US09784892
申请日：2001-02-15
申请人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
发明人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
IPC分类号： H01L2176
CPC分类号： H01L21/7621 , H01L21/3085 , H01L21/3086 , H01L21/76232
摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.
摘要翻译：一种用于产生浅沟槽隔离的半导体装置和方法。该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域。随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

3. 发明授权

US06444530B1 Process for fabricating an integrated circuit with a self-aligned contact 有权
标题翻译：用于制造具有自对准接触的集成电路的工艺
公开(公告)号：US06444530B1
公开(公告)日：2002-09-03
申请号：US09318429
申请日：1999-05-25
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76897 , H01L23/485 , H01L27/115 , H01L2924/0002 , Y10T428/12542 , Y10T428/1259 , Y10T428/12625 , Y10T428/12778 , H01L2924/00
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.
摘要翻译：在闪速存储器件中形成触点的方法利用局部互连处理技术。局部互连处理技术允许接触件与存储器单元相关联的堆叠栅极对接或重叠。接触可以包括钨。堆叠的栅极被也覆盖绝缘间隔物的阻挡层覆盖。

4. 发明授权

US5907781A Process for fabricating an integrated circuit with a self-aligned contact 失效
公开(公告)号：US5907781A
公开(公告)日：1999-05-25
申请号：US49517
申请日：1998-03-27
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L21/335
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

5. 发明授权

US06455373B1 Semiconductor device having gate edges protected from charge gain/loss 有权
标题翻译：具有防止电荷增益/损耗的栅极边缘的半导体器件
公开(公告)号：US06455373B1
公开(公告)日：2002-09-24
申请号：US09834419
申请日：2001-04-12
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).
摘要翻译：在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

6. 发明授权

US06248627B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06248627B1
公开(公告)日：2001-06-19
申请号：US09376658
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

7. 发明授权

US06475847B1 Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：使用衬垫氧化物层形成具有自对准触点的半导体器件的方法
公开(公告)号：US06475847B1
公开(公告)日：2002-11-05
申请号：US10109526
申请日：2002-03-27
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种缩小半导体器件并最小化自动掺杂问题的方法。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触，并且用作电介质层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

8. 发明授权

US06808996B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06808996B1
公开(公告)日：2004-10-26
申请号：US09376659
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

9. 发明授权

US06664191B1 Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space 有权
标题翻译：非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间
公开(公告)号：US06664191B1
公开(公告)日：2003-12-16
申请号：US09973131
申请日：2001-10-09
申请人： Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
发明人： Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
IPC分类号： H01L21302
CPC分类号： H01L27/11526 , H01L21/0337 , H01L21/0338 , H01L21/76229 , H01L21/76838 , H01L27/11531 , Y10S438/975
摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.
摘要翻译：提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。第一多晶硅层沉积在覆盖STI区域的衬底上。然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

10. 发明授权

US06420752B1 Semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：具有使用衬垫氧化物层的自对准触点的半导体器件
公开(公告)号：US06420752B1
公开(公告)日：2002-07-16
申请号：US09502163
申请日：2000-02-11
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种用于最小化自动掺杂问题的半导体器件。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

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