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1. 发明申请

US20050141683A1 Control and monitoring telecommunication system and method of setting a modulation method 失效
标题翻译：控制和监测电信系统和设置调制方法
公开(公告)号：US20050141683A1
公开(公告)日：2005-06-30
申请号：US11018355
申请日：2004-12-22
申请人： Yoshikazu Ishii , Setsuo Arita , Yuji Ichinose , Nao Saito , Daisuke Sinma , Yasuhiro Nakatsuka
发明人： Yoshikazu Ishii , Setsuo Arita , Yuji Ichinose , Nao Saito , Daisuke Sinma , Yasuhiro Nakatsuka
IPC分类号： H04N7/18 , H04J1/00 , H04L1/00 , H04L27/00 , H04M11/00
CPC分类号： H04L5/0094 , H04L5/0007 , H04L5/0037 , H04L5/0046 , H04L5/006
摘要： Using a network in which one master station modem 105 and multiple slave station modem 106, 107, 108 are physically connected by rudder connection or bus connection with a telecommunication line 121, the measurement result of the S/N ratio between the master station and slave stations is once collected in the master station at the initialization stage, pairs of the modulation method, by which all modems can demodulate at high probability, and transmission voltage are calculated based on this data, and the calculation is transmitted to all slave stations; and at a normal transmission stage, information regarding the coordination and control of the network is transmitted in accordance with this setting. Thus, one-to-multi communication is realized, guaranteeing an access right.
摘要翻译：使用其中一个主站调制解调器105和多个从站调制解调器106,107,108通过与电信线路121的舵连接或总线连接物理连接的网络，主站和从站之间的S / N比的测量结果在初始化阶段，主站一旦收集站，则可以根据该数据计算出所有调制解调器可以以高概率解调的调制方式对和传输电压，并将计算发送到所有从站; 并且在正常发送阶段，根据该设置发送关于网络的协调和控制的信息。因此，实现一对多通信，保证访问权限。

2. 发明授权

US07570748B2 Control and monitoring telecommunication system and method of setting a modulation method 失效
标题翻译：控制和监测电信系统和设置调制方法
公开(公告)号：US07570748B2
公开(公告)日：2009-08-04
申请号：US11018355
申请日：2004-12-22
申请人： Yoshikazu Ishii , Setsuo Arita , Yuji Ichinose , Nao Saito , Daisuke Sinma , Yasuhiro Nakatsuka
发明人： Yoshikazu Ishii , Setsuo Arita , Yuji Ichinose , Nao Saito , Daisuke Sinma , Yasuhiro Nakatsuka
IPC分类号： H04M11/06
CPC分类号： H04L5/0094 , H04L5/0007 , H04L5/0037 , H04L5/0046 , H04L5/006
摘要： Using a network in which one master station modem 105 and multiple slave station modem 106, 107, 108 are physically connected by rudder connection or bus connection with a telecommunication line 121, the measurement result of the S/N ratio between the master station and slave stations is once collected in the master station at the initialization stage, pairs of the modulation method, by which all modems can demodulate at high probability, and transmission voltage are calculated based on this data, and the calculation is transmitted to all slave stations; and at a normal transmission stage, information regarding the coordination and control of the network is transmitted in accordance with this setting. Thus, one-to-multi communication is realized, guaranteeing an access right.
摘要翻译：使用其中一个主站调制解调器105和多个从站调制解调器106,107,108通过与电信线路121的舵连接或总线连接物理连接的网络，主站和从站之间的S / N比的测量结果在初始化阶段，主站一旦收集站，则可以根据该数据计算出所有调制解调器可以以高概率解调的调制方式对和传输电压，并将计算发送到所有从站; 并且在正常发送阶段，根据该设置发送关于网络的协调和控制的信息。因此，实现一对多通信，保证访问权限。

3. 发明授权

US08578135B2 Apparatus for calculating and prefetching a branch target address 有权
标题翻译：用于计算和预取分支目标地址的装置
公开(公告)号：US08578135B2
公开(公告)日：2013-11-05
申请号：US13423145
申请日：2012-03-16
申请人： Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
发明人： Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/382
摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
摘要翻译：能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。

4. 发明授权

US08423661B2 Packet communication device, packet communication system, packet communication module, data processor, and data transfer system 有权
公开(公告)号：US08423661B2
公开(公告)日：2013-04-16
申请号：US12873893
申请日：2010-09-01
申请人： Hiroshi Arita , Yasuhiro Nakatsuka , Yasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
发明人： Hiroshi Arita , Yasuhiro Nakatsuka , Yasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
IPC分类号： G06F13/00
CPC分类号： H04L47/6255 , H04L12/44 , H04L47/10 , H04L47/2458 , H04L47/30 , H04L47/522 , H04L49/205 , H04L49/3018 , H04L49/351
摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.

5. 发明授权

US07630807B2 Vehicle control system 有权
标题翻译：车辆控制系统
公开(公告)号：US07630807B2
公开(公告)日：2009-12-08
申请号：US11094660
申请日：2005-03-31
申请人： Kentaro Yoshimura , Kohei Sakurai , Nobuyasu Kanekawa , Yuichiro Morita , Yoshiaki Takahashi , Kenichi Kurosawa , Toshimichi Minowa , Masatoshi Hoshino , Yasuhiro Nakatsuka , Kotaro Shimamura , Kunihiko Tsunedomi , Shoji Sasaki
发明人： Kentaro Yoshimura , Kohei Sakurai , Nobuyasu Kanekawa , Yuichiro Morita , Yoshiaki Takahashi , Kenichi Kurosawa , Toshimichi Minowa , Masatoshi Hoshino , Yasuhiro Nakatsuka , Kotaro Shimamura , Kunihiko Tsunedomi , Shoji Sasaki
IPC分类号： G05D3/00
CPC分类号： B60W30/00 , B60K6/46 , B60K6/52 , B60L3/0023 , B60L3/003 , B60L3/0076 , B60L3/0092 , B60L15/2009 , B60L2240/12 , B60L2240/20 , B60L2240/24 , B60L2240/423 , B60L2250/26 , B60T7/12 , B60W10/04 , B60W10/06 , B60W10/08 , B60W10/10 , B60W10/18 , B60W10/20 , B60W20/00 , B60W40/08 , B60W40/10 , B60W50/02 , B60W50/0225 , B60W50/04 , B60W2510/20 , B60W2510/202 , B60W2520/14 , B60W2540/10 , B60W2540/12 , B60W2550/20 , B62D5/046 , B62D5/0481 , B62D6/00 , G06F11/0796 , Y02T10/6217 , Y02T10/6265 , Y02T10/6286 , Y02T10/645 , Y02T10/72 , Y02T10/7275 , Y02T90/16
摘要： A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network. The actuator controller includes a control target value generating unit for generating a control target value based on the sensor signals taken in by the sensor controller and received by the actuator controller via the network when the control target value generated by the command controller is abnormal, and controls the actuator in accordance with the control target value generated by the control target value generating unit.
摘要翻译：一种车辆控制系统，可以通过简化的ECU配置和低成本确保高可靠性，实时处理和可扩展性，通过整个系统中的协调备份错误，而不会增加单个控制器的冗余程度，超出最不必要的范围水平。车辆控制系统包括：传感器控制器，用于接收指示车辆的状态变量的传感器信号和从驾驶员施加的操作量;命令控制器，用于基于由传感器控制器接收的传感器信号产生控制目标值; 以及致动器控制器，用于从命令控制器接收控制目标值并操作致动器来控制车辆，这三个控制器经由网络互连。执行器控制器包括控制目标值产生单元，用于当由指令控制器产生的控制目标值异常时，基于由传感器控制器接收并由致动器控制器经由网络接收的传感器信号产生控制目标值;以及根据由控制目标值产生单元产生的控制目标值来控制致动器。

6. 发明申请

US20080177855A1 Packet communication apparatus 审中-公开
标题翻译：分组通信装置
公开(公告)号：US20080177855A1
公开(公告)日：2008-07-24
申请号：US12076686
申请日：2008-03-21
申请人： Hiroshi Arita , Yasuhiro Nakatsuka , Kotaro Shimamura , Yasuwo Watanabe
发明人： Hiroshi Arita , Yasuhiro Nakatsuka , Kotaro Shimamura , Yasuwo Watanabe
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/90 , H04L69/161 , H04L69/162 , H04L69/22
摘要： A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.
摘要翻译：包括CPU，存储器和分组通信电路的分组通信装置充当远程监视和控制受控对象的网络连接受控对象和网络终端之间的接口，并且在受控对象和网络终端还包括作为用于执行校验和计算以检查分组错误和复制操作的硬件单元的复制和操作单元。复制和操作单元在存储器中形成并由分组通信电路使用的发送缓冲器/接收缓冲器与由通信处理程序使用的工作区域之间同时执行分组数据复制操作和校验和计算，从而减少加载CPU并增加通信处理速度。

7. 发明授权

US07142213B2 Graphics drawing device and method 有权
标题翻译：图形绘图装置及方法
公开(公告)号：US07142213B2
公开(公告)日：2006-11-28
申请号：US10822672
申请日：2004-04-13
申请人： Yasuhiro Nakatsuka , Keisuke Nakashima , Shigeru Matsuo , Masahisa Narita , Koyo Katsura , Hidehito Takewa , Tomoaki Aoki
发明人： Yasuhiro Nakatsuka , Keisuke Nakashima , Shigeru Matsuo , Masahisa Narita , Koyo Katsura , Hidehito Takewa , Tomoaki Aoki
IPC分类号： G06F15/00 , G06T1/20 , G09G5/36
CPC分类号： G06T15/40 , G06T1/20
摘要： In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.
摘要翻译：在执行图像数据的处理（显示和输出）的装置和系统中，保持图像数据的存储器和处理图像数据的处理器之间传送的数据量受到限制，从而可以在高处处理大量的数据速度。

8. 发明申请

US20060202992A1 Data processing apparatus and shading apparatus 审中-公开
公开(公告)号：US20060202992A1
公开(公告)日：2006-09-14
申请号：US11432350
申请日：2006-05-12
申请人： Yasuhiro Nakatsuka , Shigeru Matsuo , Jun Satoh , Masanori Miyoshi , Koyo Katsura , Takashi Sone
发明人： Yasuhiro Nakatsuka , Shigeru Matsuo , Jun Satoh , Masanori Miyoshi , Koyo Katsura , Takashi Sone
IPC分类号： G06T15/50 , G06T15/60
CPC分类号： G06T1/60 , G06T11/40 , G06T15/50 , G06T15/80
摘要： In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.

9. 发明授权

US06717583B2 Data processor having unified memory architecture providing priority memory access 失效
标题翻译：数据处理器具有统一的存储器架构，提供优先存储器
公开(公告)号：US06717583B2
公开(公告)日：2004-04-06
申请号：US09991705
申请日：2001-11-26
申请人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
发明人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
IPC分类号： G06F15167
CPC分类号： G09G5/001 , G06F13/1673 , G06F13/18 , G09G5/02 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/02 , G09G2360/121 , G09G2360/125 , G09G2360/128
摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
摘要翻译：为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求当CPU总线310的访问结束时，存储器控制器400重新启动在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

10. 发明授权

US6167497A Data processing apparatus and register address translation method thereof 失效
标题翻译：数据处理装置及其寄存器地址转换方法
公开(公告)号：US6167497A
公开(公告)日：2000-12-26
申请号：US871978
申请日：1997-06-10
申请人： Yasuhiro Nakatsuka , Koyo Katsura
发明人： Yasuhiro Nakatsuka , Koyo Katsura
IPC分类号： G06F9/38 , G06F9/30 , G06F9/318 , G06F9/34 , G06F12/00 , G06F12/02
CPC分类号： G06F9/30138
摘要： A data processing apparatus includes physical registers larger in number than logical registers specified by a register specification field of an instruction executed by the apparatus. The physical registers are classified into a plurality of banks. In response to a particular instruction, an execution control section supplies a register address converter with bank information to select a bank of the physical register. The converter stores the bank information in a bank register. Receiving logical register address information specified by the register specification field of the instruction, the address converter adds the bank information set to the bank register to at least a portion of the logical register address information, thereby producing a physical register address which can specify any one of the physical registers.
摘要翻译：数据处理装置包括数量大于由装置执行的指令的寄存器指定字段指定的逻辑寄存器的物理寄存器。物理寄存器分为多个存储体。响应于特定指令，执行控制部分向寄存器地址转换器提供银行信息以选择一个物理寄存器组。转换器将银行信息存储在银行寄存器中。接收由指令的寄存器指定字段指定的逻辑寄存器地址信息，地址转换器将存储体信息设置添加到存储体寄存器至少部分逻辑寄存器地址信息，从而产生一个物理寄存器地址，的物理寄存器。

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