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1. 发明授权

US06954206B2 Data processor having unified memory architecture using register to optimize memory access 失效
标题翻译：具有使用寄存器的统一存储器架构的数据处理器来优化存储器
公开(公告)号：US06954206B2
公开(公告)日：2005-10-11
申请号：US10669562
申请日：2003-09-25
申请人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
发明人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
IPC分类号： G06F13/14 , G06F13/16 , G06F13/18 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/36 , G09G5/39
CPC分类号： G09G5/001 , G06F13/1673 , G06F13/18 , G09G5/02 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/02 , G09G2360/121 , G09G2360/125 , G09G2360/128
摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
摘要翻译：为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求由存储器200。当CPU总线310的访问结束时，存储器控制器400重启在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

2. 发明授权

US06717583B2 Data processor having unified memory architecture providing priority memory access 失效
标题翻译：数据处理器具有统一的存储器架构，提供优先存储器
公开(公告)号：US06717583B2
公开(公告)日：2004-04-06
申请号：US09991705
申请日：2001-11-26
申请人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
发明人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
IPC分类号： G06F15167
CPC分类号： G09G5/001 , G06F13/1673 , G06F13/18 , G09G5/02 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/02 , G09G2360/121 , G09G2360/125 , G09G2360/128
摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
摘要翻译：为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求当CPU总线310的访问结束时，存储器控制器400重新启动在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

3. 发明申请

US20050264574A1 Data processor having unified memory architecture using register to optimize memory access 有权
标题翻译：具有使用寄存器的统一存储器架构的数据处理器来优化存储器访问
公开(公告)号：US20050264574A1
公开(公告)日：2005-12-01
申请号：US11182944
申请日：2005-07-18
申请人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
发明人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
IPC分类号： G06F13/14 , G06F13/16 , G06F13/18 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/36 , G09G5/39
CPC分类号： G09G5/001 , G06F13/1673 , G06F13/18 , G09G5/02 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/02 , G09G2360/121 , G09G2360/125 , G09G2360/128
摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
摘要翻译：为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求当CPU总线310的访问结束时，存储器控制器400重新启动在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

4. 发明授权

US06333745B1 Data processor having unified memory architecture providing priority memory access 失效
标题翻译：数据处理器具有统一的存储器架构，提供优先存储器访问
公开(公告)号：US06333745B1
公开(公告)日：2001-12-25
申请号：US08942689
申请日：1997-09-29
申请人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
发明人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
IPC分类号： G06F1316
CPC分类号： G09G5/001 , G06F13/1673 , G06F13/18 , G09G5/02 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/02 , G09G2360/121 , G09G2360/125 , G09G2360/128
摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory is generated from the CPU, the memory controller holds it once, requests the display controller to stop the access to the memory which is in execution, when data to the access executed already is transferred from the memory, holds it, and transfers the access request from the CPU bus which is held by the memory. When the access from the CPU bus ends, the memory controller restarts the access stopped in the display controller and passes the held data to the display controller.
摘要翻译：为了减少由于使用主存储器的一部分而将数据处理器的处理性能降低为显示帧缓冲器，当从CPU生成对存储器的访问请求时，存储器控制器保持一次，请求显示控制器停止对正在执行的存储器的访问，当已经从执行的访问的数据的数据从存储器传送时，保持它，并且从由存储器保存的CPU总线传送访问请求。当CPU总线的访问结束时，存储器控制器重新启动显示控制器中停止的访问，并将保持的数据传送到显示控制器。

5. 发明授权

US07333116B2 Data processor having unified memory architecture using register to optimize memory access 有权
标题翻译：具有使用寄存器的统一存储器架构的数据处理器来优化存储器访问
公开(公告)号：US07333116B2
公开(公告)日：2008-02-19
申请号：US11182944
申请日：2005-07-18
申请人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
发明人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
IPC分类号： G09G5/39 , G09G5/36 , G06F13/14 , G06F15/167
CPC分类号： G09G5/001 , G06F13/1673 , G06F13/18 , G09G5/02 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/02 , G09G2360/121 , G09G2360/125 , G09G2360/128
摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
摘要翻译：为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求由存储器200。当CPU总线310的访问结束时，存储器控制器400重启在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

6. 发明授权

US06600492B1 Picture processing apparatus and picture processing method 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US06600492B1
公开(公告)日：2003-07-29
申请号：US09292375
申请日：1999-04-15
申请人： Tetsuya Shimomura , Shigeru Matsuo , Kazuyoshi Koga , Koyo Katsura , Yasuhiro Nakatsuka , Kazushige Yamagishi
发明人： Tetsuya Shimomura , Shigeru Matsuo , Kazuyoshi Koga , Koyo Katsura , Yasuhiro Nakatsuka , Kazushige Yamagishi
IPC分类号： G06T1500
CPC分类号： G06T1/60
摘要： In order to assure that a plurality of circuits such as a CPU I/F circuit, a rendering circuit, a video input circuit and a display circuit, which are each required to always complete a processing within a prescribed time, are each assured the ability to make as many accesses to a memory as required to complete the processing within the prescribed time, it is necessary to arbitrate a contention for an access to the memory through an internal bus among the circuits by employing a bus control circuit wherein priority levels assigned to the circuits to make an access to the internal bus are dynamically changed by comparing degrees of access urgency among the circuits. In this way, circuits that each have to always complete theirs processing within a prescribed time are assured the ability to make as many accesses to the memory as required to complete the processing within the prescribed time even if a plurality of such circuits do exist.
摘要翻译：为了确保在规定时间内需要总是完成处理的多个电路，例如CPU I / F电路，再现电路，视频输入电路和显示电路，都能确保能力为了在规定的时间内对存储器进行尽可能多的访问以完成处理，有必要通过使用总线控制电路来通过内部总线来仲裁访问存储器的争用，其中优先级分配给通过比较电路之间的访问紧急程度来动态地改变访问内部总线的电路。以这种方式，每个必须总是在规定时间内完成它们的处理的电路确保了即使存在多个这样的电路，也可以在规定的时间内完成处理所需的存储器的访问的能力。

7. 发明申请

US20050062749A1 Memory access methods in a unified memory system 有权
标题翻译：内存访问方法在统一的内存系统中
公开(公告)号：US20050062749A1
公开(公告)日：2005-03-24
申请号：US10983757
申请日：2004-11-09
申请人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
发明人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
IPC分类号： G06F13/16 , G06F3/153 , G06F12/00 , G06F12/04 , G09G5/39 , G06F15/167 , G06F13/00
CPC分类号： G09G5/39 , G09G2360/125
摘要： The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
摘要翻译：多媒体数据处理系统的基本部分包括CPU 1100，图像显示单元2100，统一存储器1200，系统总线1920和连接到系统总线的设备1300,1400和1500。在这种配置中，CPU形成在安装在包括指令处理单元1110和显示控制单元1140的单个硅晶片上的LSI上。主存储区域1210和显示区域1220存储在统一存储器内。与用于连接LSI和输入/输出设备的系统总线无关地提供用于连接对应的LSI和统一存储器的统一存储器端口1910。统一的存储器端口可以比系统总线更快地驱动。

8. 发明授权

US07557809B2 Memory access methods in a unified memory system 有权
标题翻译：内存访问方法在统一的内存系统中
公开(公告)号：US07557809B2
公开(公告)日：2009-07-07
申请号：US10983757
申请日：2004-11-09
申请人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
发明人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
IPC分类号： G06F13/14 , G09G5/39 , G06F15/167
CPC分类号： G09G5/39 , G09G2360/125
摘要： The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
摘要翻译：多媒体数据处理系统的基本部分包括CPU 1100，图像显示单元2100，统一存储器1200，系统总线1920和连接到系统总线的设备1300,1400和1500。在这种配置中，CPU形成在安装在包括指令处理单元1110和显示控制单元1140的单个硅晶片上的LSI上。主存储区域1210和显示区域1220存储在统一存储器内。与用于连接LSI和输入/输出设备的系统总线无关地提供用于连接对应的LSI和统一存储器的统一存储器端口1910。统一的存储器端口可以比系统总线更快地驱动。

9. 发明授权

US06839063B2 Memory access methods in a unified memory system 有权
标题翻译：内存访问方法在统一的内存系统中
公开(公告)号：US06839063B2
公开(公告)日：2005-01-04
申请号：US09791817
申请日：2001-02-26
申请人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
发明人： Yasuhiro Nakatsuka , Tetsuya Shimomura , Manabu Jyou , Yuichiro Morita , Takashi Hotta , Kazushige Yamagishi , Yutaka Okada
IPC分类号： G06F13/16 , G06F3/153 , G06F12/00 , G06F12/04 , G09G5/39 , G06F13/372
CPC分类号： G09G5/39 , G09G2360/125
摘要： The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

10. 发明授权

US06745279B2 Memory controller 失效
标题翻译：内存控制器
公开(公告)号：US06745279B2
公开(公告)日：2004-06-01
申请号：US09962257
申请日：2001-09-26
申请人： Yuichiro Morita , Manabu Jyou , Yasuhiro Nakatsuka , Tetsuya Shimomura , Yutaka Okada , Kazushige Yamagishi
发明人： Yuichiro Morita , Manabu Jyou , Yasuhiro Nakatsuka , Tetsuya Shimomura , Yutaka Okada , Kazushige Yamagishi
IPC分类号： G06F1200
CPC分类号： G06F13/161
摘要： A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.
摘要翻译：公开了一种存储器控制器，其中在从设备接收到访问请求时，存储器控制器基于访问请求以预定的存储器周期来激活由第一存储体的行地址指定的页面。之后，在对第一个银行的页面的读取访问之前，接下来要访问的第二个银行被预充电。在通过读取操作访问第一存储体之后，由于通过图形处理从第一存储体到第二存储体的访问发生页面错误的情况下，存储器控制器立即激活第二存储体而不进行预充电。

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