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1. 发明申请

US20130105913A1 Current Control Semiconductor Element and Control Device Using the Same 有权
标题翻译：电流控制半导体元件及其使用方法
公开(公告)号：US20130105913A1
公开(公告)日：2013-05-02
申请号：US13807278
申请日：2011-06-02
申请人： Teppei Hirotsu , Nobuyasu Kanekawa , Itaru Tanabe
发明人： Teppei Hirotsu , Nobuyasu Kanekawa , Itaru Tanabe
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L27/0211 , H01L27/0266 , H01L29/41758 , H01L29/4238 , H03K17/145
摘要： This invention provides a current control semiconductor element in which dependence of a sense ratio on a temperature distribution is eliminated and the accuracy of current detection using a sense MOSFET can be improved, and to provide a control device using the current control semiconductor element. The current control semiconductor element 1 includes a main MOSFET 7 that drives a current and a sense MOSFET 8 that is connected to the main MOSFET in parallel and detects a current shunted from a current of the main MOSFET. The main MOSFET is formed using a multi-finger MOSFET that has a plurality of channels and is arranged in a row. When a distance between the center of the multi-finger MOSFET 7 and a channel located farthest from the center of the multi-finger MOSFET 7 is indicated by L, a channel that is located closest to a position distant by a distance of (L/(√3)) from the center of the multi-finger MOSFET is used as a channel for the sense MOSFET 8.
摘要翻译：本发明提供了一种电流控制半导体元件，其中消除了感测比对温度分布的依赖性，并且可以提高使用感测MOSFET的电流检测的精度，并提供使用电流控制半导体元件的控制装置。电流控制半导体元件1包括驱动电流的主MOSFET 7和并联连接到主MOSFET的感测MOSFET 8，并且检测从主MOSFET的电流分流的电流。主MOSFET使用具有多个通道并排列成一排的多指MOSFET形成。当多指MOSFET 7的中心与距离多指MOSFET 7的中心最远的通道之间的距离由L表示时，位于最靠近距离为（L / （√3））从多指MOSFET的中心用作感测MOSFET 8的通道。

2. 发明申请

US20070180317A1 ERROR CORRECTION METHOD 有权
标题翻译：错误校正方法
公开(公告)号：US20070180317A1
公开(公告)日：2007-08-02
申请号：US11623441
申请日：2007-01-16
申请人： Teppei HIROTSU , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
发明人： Teppei HIROTSU , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
IPC分类号： G06F11/00
CPC分类号： G06F11/1407
摘要： This method is an error correction method such that, when an error is detected in a CPU with pipeline struct, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
摘要翻译：该方法是一种错误校正方法，使得当在具有流水线结构的CPU中检测到错误时，通过延迟的寄存器文件来恢复寄存器文件的内容，该延迟寄存器文件保持在之前正确执行的[指令N]的执行完成状态该错误和执行作为[指令N]的下一条指令的[指令N + 1]的指令的回滚控制。该方法收集CPU内存在的任意Flip-Flops的奇偶校验结果，并检测出错误。结果，寄存器文件的内容被恢复到可能由错误导致故障的指令范围之前的指令执行完成状态，并且可以从可能由错误发生故障的指令范围的开始滚转指令。

3. 发明申请

US20050172110A1 Information processing apparatus 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20050172110A1
公开(公告)日：2005-08-04
申请号：US11046453
申请日：2005-01-28
申请人： Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
发明人： Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
IPC分类号： G06F9/38 , G06F9/30 , G06F9/32 , G06F9/42 , G06F9/46 , G06F9/48
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/382
摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
摘要翻译：能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。

4. 发明授权

US09146567B2 Current control device 有权
标题翻译：电流控制装置
公开(公告)号：US09146567B2
公开(公告)日：2015-09-29
申请号：US13985627
申请日：2012-02-21
申请人： Teppei Hirotsu , Nobuyasu Kanekawa , Ryosuke Ishida
发明人： Teppei Hirotsu , Nobuyasu Kanekawa , Ryosuke Ishida
IPC分类号： H02M3/157 , G05F1/10 , H02P29/02 , H02M7/538 , H01F7/18 , H02M1/32
CPC分类号： G05F1/10 , H01F2007/1888 , H02M1/32 , H02M7/53803 , H02P29/0241 , H02P29/0243 , H02P29/032
摘要： A current control device capable of performing widely applicable failure detection without a motor rotation speed sensor is provided. A current control semiconductor element includes, on a same semiconductor chip, a transistor that drives load, a current detection circuit that detects current of the load, a compensator that calculates an on-duty of the transistor from a current command value and a current value output from the current detection circuit, and a PWM timer that generates a pulse turning on the transistor on the basis of the on-duty. A microcontroller sends the current command value to the current control semiconductor element, receives the current value output from the current detection circuit and the on-duty output from the compensator from the current control semiconductor element, and detects failure of the current control semiconductor element on the basis of the received current value and on-duty.
摘要翻译：提供一种能够在没有马达转速传感器的情况下执行广泛应用的故障检测的电流控制装置。电流控制半导体元件在相同的半导体芯片上包括驱动负载的晶体管，检测负载电流的电流检测电路，从电流指令值和电流值计算晶体管的占空比的补偿器来自电流检测电路的输出;以及PWM定时器，其基于占空比产生导通晶体管的脉冲。微控制器将电流指令值发送到电流控制半导体元件，从电流控制半导体元件接收从电流检测电路输出的电流值和来自补偿器的占空比输出，并检测电流控制半导体元件的故障所接受的现值和值班的依据。

5. 发明申请

US20130320948A1 Current Control Device 有权
标题翻译：电流控制装置
公开(公告)号：US20130320948A1
公开(公告)日：2013-12-05
申请号：US13985627
申请日：2012-02-21
申请人： Teppei Hirotsu , Nobuyasu Kanekawa , Ryosuke Ishida
发明人： Teppei Hirotsu , Nobuyasu Kanekawa , Ryosuke Ishida
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , H01F2007/1888 , H02M1/32 , H02M7/53803 , H02P29/0241 , H02P29/0243 , H02P29/032
摘要： A current control device capable of performing widely applicable failure detection without a motor rotation speed sensor is provided. A current control semiconductor element includes, on a same semiconductor chip, a transistor that drives load, a current detection circuit that detects current of the load, a compensator that calculates an on-duty of the transistor from a current command value and a current value output from the current detection circuit, and a PWM timer that generates a pulse turning on the transistor on the basis of the on-duty. A microcontroller sends the current command value to the current control semiconductor element, receives the current value output from the current detection circuit and the on-duty output from the compensator from the current control semiconductor element, and detects failure of the current control semiconductor element on the basis of the received current value and on-duty.
摘要翻译：提供一种能够在没有马达转速传感器的情况下执行广泛应用的故障检测的电流控制装置。电流控制半导体元件在相同的半导体芯片上包括驱动负载的晶体管，检测负载电流的电流检测电路，从电流指令值和电流值计算晶体管的占空比的补偿器来自电流检测电路的输出;以及PWM定时器，其基于占空比产生导通晶体管的脉冲。微控制器将电流指令值发送到电流控制半导体元件，从电流控制半导体元件接收从电流检测电路输出的电流值和来自补偿器的占空比输出，并检测电流控制半导体元件的故障所接受的现值和值班的依据。

6. 发明授权

US08578135B2 Apparatus for calculating and prefetching a branch target address 有权
标题翻译：用于计算和预取分支目标地址的装置
公开(公告)号：US08578135B2
公开(公告)日：2013-11-05
申请号：US13423145
申请日：2012-03-16
申请人： Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
发明人： Teppei Hirotsu , Yuuichi Abe , Takeshi Kataoka , Yasuhiro Nakatsuka
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/382
摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
摘要翻译：能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。

7. 发明授权

US07752527B2 Microcontroller and RAM 失效
标题翻译：微控制器和RAM
公开(公告)号：US07752527B2
公开(公告)日：2010-07-06
申请号：US11604806
申请日：2006-11-28
申请人： Hiromichi Yamada , Teppei Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
发明人： Hiromichi Yamada , Teppei Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
IPC分类号： G11C29/00
CPC分类号： G06F11/167 , G06F11/08 , G06F11/183
摘要： A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.
摘要翻译：提供了一种微控制器，其中硬件的增加被抑制，并且可以提高对RAM的软件错误的数据校正能力。执行根据程序的处理的微控制器包括CPU和RAM，用于存储由CPU处理的数据，其中在RAM中定义复用区域，并且当这些区域被访问时，访问由CPU输出的地址和执行通过向CPU输出的地址添加或减去某个值而获得的地址的复制访问。通过这种方式，可以将相同的数据存储在多个区域中，并且可以提高可靠性。

8. 发明申请

US20090024777A1 ARBITER AND ARBITRATION METHOD OF MULTIPLE DATA ACCESSES 失效
标题翻译：多数据访问的ARBITER和仲裁方法
公开(公告)号：US20090024777A1
公开(公告)日：2009-01-22
申请号：US12134038
申请日：2008-06-05
申请人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
发明人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
IPC分类号： G06F13/366
CPC分类号： G06F13/366
摘要： There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.
摘要翻译：提供了一种技术，即使在高优先级访问请求和低请求访问请求被同时生成的情况下，也可以抑制高优先级访问处理的平均延迟增加来降低低优先级访问的平均处理时间，共享访问处理单元和高优先级访问被连续生成。并且，提供了一种访问仲裁设备，包括：发布的访问请求保留单元; 第一间隔确定电路; 和第二间隔确定电路。在第一间隔确定电路确定在发出的访问处理和最先进的访问处理之间产生间隔的情况下，并且第二间隔确定电路确定在所发行的访问处理和第二先前的访问请求之间不产生间隔，最先进的访问请求和第二个访问请求的优先顺序被改变。

9. 发明授权

US09170587B2 Current control semiconductor element and control device using the same 有权
标题翻译：电流控制半导体元件及使用其的控制装置
公开(公告)号：US09170587B2
公开(公告)日：2015-10-27
申请号：US13818107
申请日：2011-08-01
申请人： Teppei Hirotsu , Nobuyasu Kanekawa , Itaru Tanabe
发明人： Teppei Hirotsu , Nobuyasu Kanekawa , Itaru Tanabe
IPC分类号： G05F1/46 , G05F1/10 , H02P3/22 , H02P6/24
CPC分类号： G05F1/10 , H02P3/22 , H02P6/24
摘要： This invention provides a current control semiconductor element that can detect a current with high accuracy in a single IC chip by dynamically correcting changes in a gain a and an offset b, and a control device that uses the current control semiconductor element, the current control semiconductor element has a transistor 4, a current-to-voltage conversion circuit 22 and an AD converter 23 on the same semiconductor chip. A reference current generation circuit 6 superimposes a current pulse Ic on a current of a load 2 and changes a voltage digital value to be output from the AD converter. A gain/offset corrector 8 executes signal processing on change in the voltage digital value caused by the reference current generation circuit 6 to dynamically acquire the gain a and the offset b that are used in an equation that indicates a linear relationship between the voltage digital value output from the AD converter 23 and the current digital value of the load. A current digital value calculator 12 uses the gain and the offset acquired by the gain/offset corrector 8 to correct the voltage value output from the AD converter.
摘要翻译：本发明提供了一种电流控制半导体元件，其可以通过动态地校正增益a和偏移b的变化，以及使用电流控制半导体元件的控制装置，电流控制半导体，可以在单个IC芯片中以高精度检测电流元件在相同的半导体芯片上具有晶体管4，电流 - 电压转换电路22和AD转换器23。参考电流产生电路6将电流脉冲Ic叠加在负载2的电流上，并改变要从AD转换器输出的电压数字值。增益/偏移校正器8对由参考电流产生电路6引起的电压数字值的变化执行信号处理，以动态地获取在表示电压数字值之间的线性关系的方程式中使用的增益a和偏移量b AD转换器23的输出和负载的当前数字值。当前数字值计算器12使用由增益/偏移校正器8获取的增益和偏移来校正从AD转换器输出的电压值。

10. 发明授权

US09154033B2 Current control semiconductor device and control device using the same 有权
标题翻译：电流控制半导体器件和使用其的控制器件
公开(公告)号：US09154033B2
公开(公告)日：2015-10-06
申请号：US14130688
申请日：2012-07-03
申请人： Kenichi Hoshino , Teppei Hirotsu , Ryosuke Ishida
发明人： Kenichi Hoshino , Teppei Hirotsu , Ryosuke Ishida
IPC分类号： H03M1/14 , H02M3/157 , H03M1/06 , H03M1/12 , F02D41/20
CPC分类号： H02M3/157 , F02D2041/2024 , F02D2041/2058 , H03M1/0609 , H03M1/12
摘要： A current control semiconductor device that can detect a current with high precision within an IC of one chip by dynamically correcting a variation in a gain a and an offset b, and a control device using the semiconductor device are provided. A transistor 4, a current-voltage converter circuit 22, and an AD converter 23 are disposed on an identical semiconductor chip. Reference current generator circuits 6 and 6′ superimpose a current pulse Ic on a current of a load 2, and vary a voltage digital value output by the AD converter. A gain/offset correction unit 8 subjects a variation in a voltage digital value caused by the reference current generator circuits 6, 6′ to signal processing, and dynamically acquires gains a, a′ and offsets b, b′ in a linear relational expression of the voltage digital value output by the AD converter 23 and a current digital value of the load. A current digital value calculation unit 12 corrects a voltage value output by the AD converter with the use of the gain and the offset acquired by the gain/offset correction unit 8.
摘要翻译：提供了一种电流控制半导体器件，其通过动态地校正增益a和偏移b的变化，以及使用该半导体器件的控制装置，能够以一个芯片的IC内的高精度检测电流。晶体管4，电流 - 电压转换器电路22和AD转换器23设置在相同的半导体芯片上。参考电流发生器电路6和6'将电流脉冲Ic叠加在负载2的电流上，并且改变由AD转换器输出的电压数字值。增益/偏移校正单元8使由参考电流发生器电路6,6'引起的电压数字值的变化进行信号处理，并且以线性关系表达式动态地获取增益a，a'和偏移量b，b' 由AD转换器23输出的电压数字值和负载的当前数字值。当前数字值计算单元12利用由增益/偏移校正单元8获取的增益和偏移来校正由AD转换器输出的电压值。

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