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    • 2. 发明授权
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US5824575A
    • 1998-10-20
    • US517854
    • 1995-08-22
    • Hiromasa FujimotoHiroyuki MasatoYorito OtaTomoya Uda
    • Hiromasa FujimotoHiroyuki MasatoYorito OtaTomoya Uda
    • H01L21/338H01L29/10H01L29/808H01L29/812
    • H01L29/66863H01L29/1029H01L29/1058H01L29/66878H01L29/808H01L29/812H01L29/8128
    • After forming an n-type active layer, an n.sup.+ -type source region and an n.sup.+ -type drain region at predetermined regions of a GaAs substrate, a silicon oxide film and a silicon nitride film are deposited, and then source and drain electrodes are formed. By effecting overetching on the silicon nitride film using a resist mask formed on the silicon nitride film, an upper layer portion of the silicon oxide film at a gate electrode formation region is removed, and a carrier concentration at the active layer immediately under the gate electrode is reduced. This improves a gate/drain breakdown voltage. Thereafter, a lower layer portion of the silicon oxide film at the gate formation region is removed by wet etching, and the gate electrode is formed at this removed region. A drain breakdown voltage is improved owing to reduction of the carrier concentration only at the surface region of the active layer immediately under the gate electrode.
    • 在形成n型有源层之后,沉积在GaAs衬底,氧化硅膜和氮化硅膜的预定区域处的n +型源极区域和n +型漏极区域,然后形成源极和漏极电极 。 通过使用形成在氮化硅膜上的抗蚀剂掩模对氮化硅膜进行过蚀刻,去除在栅电极形成区域处的氧化硅膜的上层部分,并且在栅电极正下方的有源层上的载流子浓度 降低了。 这提高了栅/漏击穿电压。 此后,通过湿蚀刻除去栅极形成区域处的氧化硅膜的下层部分,并且在该去除区域处形成栅电极。 由于仅在栅电极正下方的有源层的表面区域减小载流子浓度,所以提高了漏极击穿电压。
    • 8. 发明授权
    • Semiconductor device
    • 半导体器件
    • US06812505B2
    • 2004-11-02
    • US10605019
    • 2003-09-02
    • Kaoru InoueKatsunori NishiiHiroyuki Masato
    • Kaoru InoueKatsunori NishiiHiroyuki Masato
    • H01L29737
    • H01L29/7783H01L29/045H01L29/2003H01L29/42316
    • A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.
    • 半导体器件包括:衬底; 包括形成在衬底上的GaN的缓冲层,其中:缓冲层的表面是Ga原子的c个面; 在缓冲层上形成包括GaN或InGaN的沟道层,其中:沟道层的表面是Ga或In原子的c面; 包括形成在沟道层上的AlGaN的电子给体层,其中:电子给体层的表面是Al或Ga原子的c个面; 形成在电子供体层上的源电极和漏电极; 形成在源电极和漏电极之间的包含GaN或InGaAlN的覆盖层,其中:覆盖层的表面是Ga或In原子的c面,并且覆盖层的至少一部分与电子给体层接触; 以及形成为至少一部分与盖层接触的栅电极。