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1. 发明授权

US06806513B2 Heterojunction bipolar transistor having wide bandgap material in collector 有权
标题翻译：在集电极中具有宽带隙材料的异质结双极晶体管
公开(公告)号：US06806513B2
公开(公告)日：2004-10-19
申请号：US10267342
申请日：2002-10-08
申请人： Hin Fai Chau , Clarence John Dunnrowicz , Yan Chen , Chien Ping Lee
发明人： Hin Fai Chau , Clarence John Dunnrowicz , Yan Chen , Chien Ping Lee
IPC分类号： H01L29737
CPC分类号： H01L29/0821 , H01L29/7371
摘要： The safe operating area (SOA) in a heterojunction bipolar transistor is improved by inserting a material between the collector and subcollector of the transistor with the insertion layer being a material having a wider energy bandgap than the material of the collector. The insertion layer increases the breakdown field at the collector-subcollector junction and thereby increases the Kirk effect induced breakdown voltage.
摘要翻译：通过在晶体管的集电极和子集电极之间插入材料，插入层是具有比集电极的材料更宽的能量带隙的材料来改善异质结双极晶体管中的安全工作区（SOA）。插入层增加了集电极 - 子集电极结处的击穿场，从而增加了柯克效应引起的击穿电压。

2. 发明授权

US06806512B2 InPSb/InAs BJT device and method of making 失效
标题翻译： InPSb / InAs BJT设备及其制作方法
公开(公告)号：US06806512B2
公开(公告)日：2004-10-19
申请号：US10264602
申请日：2002-10-03
申请人： Chanh Nguyen , Daniel P. Docter
发明人： Chanh Nguyen , Daniel P. Docter
IPC分类号： H01L29737
CPC分类号： H01L29/66318 , H01L29/201 , H01L29/205 , H01L29/7371
摘要： Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and &rgr;-type InAs is used to create extremely high speed bipolar devices which, due to reduced turn-on voltages, lend themselves to circuits having drastically reduced power dissipation. The described HBTs are fabricated on InAs or GaSb substrates, and include an InPSb emitter. The base includes In and As, in the form of InAs when on an InAs substrate, and as InAsSb when on a GaSb substrate. The collector may be the same as the base to form a single heterojunction bipolar transistor (SHBT) or may be the same as the emitter to form a double heterojunction bipolar transistor (DHBT). Heterojunctions preferably include a grading layer, which may be implemented by continuously changing the bulk material composition, or by forming a chirped superlattice of alternating materials. The grading layer preferably has delta doping planes near its ends to form an electrostatic gradient offsetting the quasi-electric field variation due to the changes in material composition, whereby effective conduction band offset may be substantially eliminated to facilitate speed, and valence band offset increased proportionally to enhance gain.
摘要翻译：描述了双极结晶体管（BJT）器件，特别是异质结双极晶体管（HBT）器件及其制造方法。 InPSb和rho型InAs的组合用于创建极高速双极器件，由于降低的导通电压，它们可以降低功耗大大降低的电路。描述的HBT是在InAs或GaSb衬底上制造的，并包括一个InPSb发射极。基底包括In和As，InAs在InAs衬底上，InAsSb在GaSb衬底上。集电极可以与基极相同以形成单异质结双极晶体管（SHBT），或者可以与发射极相同以形成双异质结双极晶体管（DHBT）。异质结优选包括可以通过连续改变散装材料组成或通过形成交替材料的啁啾超晶格来实现的分级层。分级层优选在其端部附近具有Δ掺杂平面以形成抵消由于材料组成的变化引起的准电场变化的静电梯度，由此可以基本上消除有效导带偏移以促进速度，并且价带偏移成比例地增加增加收益。

3. 发明授权

US06744078B2 Heterojunction structure with a charge compensation layer formed between two group III-V semiconductor layers 有权
标题翻译：具有在两个III-V族半导体层之间形成的电荷补偿层的异质结结构
公开(公告)号：US06744078B2
公开(公告)日：2004-06-01
申请号：US10187648
申请日：2002-07-03
申请人： Noboru Fukuhara , Hisashi Yamada
发明人： Noboru Fukuhara , Hisashi Yamada
IPC分类号： H01L29737
CPC分类号： H01L29/7371 , H01L29/205 , H01L29/365
摘要： A thin film crystal wafer with pn-junction comprising a first layer of a first conductivity type which is a 3-5 group compound semiconductor represented by a general formula: InxGayAlzP (0≦x≦1, 0≦y≦1, 0≦z≦, x+y+z=1), and the second layer of a first conductivity type which is a 3-5 group compound semiconductor represented by a general formula: InxGayAlZ,As (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), said second layer being made above said first layer, and at a heterojunction interface formed between said first layer and said second layer, further comprising a charge compensation layer of a first conductivity type with an impurity concentration higher than that of said first and second layers.
摘要翻译：一种具有pn结的薄膜晶体晶片，包括第一导电类型的第一层，其是由以下通式表示的3-5族化合物半导体：In x Ga y Al z P（0≤x≤1,0<= y <= 1 ，0 <= z <=，x + y + z = 1），和第一导电类型的第二层，其为由以下通式表示的3-5族化合物半导体：In x Ga y AlZ，As（0 <= x < = 1,0 <= y <= 1,0 <= z <= 1，x + y + z = 1），所述第二层在所述第一层上方形成，并且在形成在所述第一层和所述第二层，还包括具有高于所述第一和第二层的杂质浓度的第一导电类型的电荷补偿层。

4. 发明授权

US06812505B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06812505B2
公开(公告)日：2004-11-02
申请号：US10605019
申请日：2003-09-02
申请人： Kaoru Inoue , Katsunori Nishii , Hiroyuki Masato
发明人： Kaoru Inoue , Katsunori Nishii , Hiroyuki Masato
IPC分类号： H01L29737
CPC分类号： H01L29/7783 , H01L29/045 , H01L29/2003 , H01L29/42316
摘要： A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.
摘要翻译：半导体器件包括：衬底; 包括形成在衬底上的GaN的缓冲层，其中：缓冲层的表面是Ga原子的c个面; 在缓冲层上形成包括GaN或InGaN的沟道层，其中：沟道层的表面是Ga或In原子的c面; 包括形成在沟道层上的AlGaN的电子给体层，其中：电子给体层的表面是Al或Ga原子的c个面; 形成在电子供体层上的源电极和漏电极; 形成在源电极和漏电极之间的包含GaN或InGaAlN的覆盖层，其中：覆盖层的表面是Ga或In原子的c面，并且覆盖层的至少一部分与电子给体层接触; 以及形成为至少一部分与盖层接触的栅电极。

5. 发明授权

US06528828B2 Differential negative resistance HBT and process for fabricating the same 失效
标题翻译：差分负电阻HBT及其制造方法
公开(公告)号：US06528828B2
公开(公告)日：2003-03-04
申请号：US09863432
申请日：2001-05-24
申请人： Tetsuya Uemura
发明人： Tetsuya Uemura
IPC分类号： H01L29737
CPC分类号： H01L29/0821 , H01L29/1004 , H01L29/7371
摘要： A differential negative resistance element includes a heavily doped GaAs layer interposed between a collector layer of lightly doped GaAs and an emitter layer of heavily doped AlGaAs, is shared between a base region between the collector layer and the emitter layer, a base contact region and a channel region between the base region and the base contact region, and a depletion layer is developed into the channel region together with the collector voltage so as to exhibit a differential negative resistance characteristics, wherein the channel region is formed through an epitaxial growth and etching so that the manufacturer easily imparts target differential negative resistance characteristics to the channel region.
摘要翻译：差分负电阻元件包括插入在轻掺杂GaAs的集电极层和重掺杂AlGaAs的发射极层之间的重掺杂GaAs层，在集电极层和发射极层之间的基极区域，基极接触区域和在基极区域和基极接触区域之间形成沟道区域，耗尽层与集电极电压一起形成沟道区域，从而呈现差分负电阻特性，其中沟道区域通过外延生长和蚀刻形成制造商容易将目标差分负电阻特性赋予通道区域。

6. 发明授权

US06399971B1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06399971B1
公开(公告)日：2002-06-04
申请号：US09191543
申请日：1998-11-13
申请人： Hisao Shigematsu , Kenji Imanishi , Hitoshi Tanaka
发明人： Hisao Shigematsu , Kenji Imanishi , Hitoshi Tanaka
IPC分类号： H01L29737
CPC分类号： H01L29/66318 , H01L29/1004 , H01L29/201 , H01L29/205 , H01L29/207 , H01L29/42304 , H01L29/7371 , H01L31/03046
摘要： The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1−xAsySb1−y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
摘要翻译：半导体器件包括集电极层14; 具有连接到集电极层14的一个表面的掺碳GaxIn1-xAsySb1-y层的基极层16; 连接在基底层16的另一个表面上的发射极层18; 与基底层16电连接的碳掺杂GaAsSb层的基极接触层30; 以及形成在基极接触层30上的基极32.这种结构的半导体器件可以具有大大降低的基极电阻RB，由此基于InP / InGaAs的HBT的基于InP / GaInAsSb的HBT可以具有更高的最大振荡频率fmax。由于碳掺杂半导体层，半导体器件可以具有更高的可靠性。

7. 发明授权

US06313488B1 Bipolar transistor having a low doped drift layer of crystalline SiC 有权
标题翻译：具有晶体SiC的低掺杂漂移层的双极晶体管
公开(公告)号：US06313488B1
公开(公告)日：2001-11-06
申请号：US09333296
申请日：1999-06-15
申请人： Mietek Bakowski , Bo Breitholtz , Ulf Gustafsson , Lennart Zdansky
发明人： Mietek Bakowski , Bo Breitholtz , Ulf Gustafsson , Lennart Zdansky
IPC分类号： H01L29737
CPC分类号： H01L29/1004 , H01L29/1608 , H01L29/2003 , H01L29/267 , H01L29/7371 , H01L29/739
摘要： A bipolar transistor having at least a low doped drift layer (14) of crystalline SiC comprises at least one first layer (13) of a semi-conductor material having a wider energy gap between the conduction band and the valence band than an adjacent layer (14) of SiC.
摘要翻译：具有晶体SiC的至少低掺杂漂移层（14）的双极晶体管包括半导体材料的至少一个第一层（13），其在导带和价带之间具有比相邻层更宽的能隙（ 14）。

8. 发明授权

US06797996B1 Compound semiconductor device and method for fabricating the same 失效
标题翻译：化合物半导体器件及其制造方法
公开(公告)号：US06797996B1
公开(公告)日：2004-09-28
申请号：US10445035
申请日：2003-05-27
申请人： Masahiro Hikita , Manabu Yanagihara , Tuyoshi Tanaka
发明人： Masahiro Hikita , Manabu Yanagihara , Tuyoshi Tanaka
IPC分类号： H01L29737
CPC分类号： H01L29/66318 , H01L29/0821 , H01L29/1004 , H01L29/365 , H01L29/7371
摘要： A compound semiconductor device includes an emitter layer, a base layer which is in contact with the emitter layer and formed of a first compound semiconductor, a collector layer which is in contact with the base layer and formed of a second compound semiconductor having a wider bandgap than that of the first compound semiconductor. In the device, a delta doped layer having a higher concentration of an impurity than that of the collector layer is formed at the heterojunction interface between the collector layer and the base layer or in a region of the collector layer located at about 10 nm or less from the heterojunction interface with the base layer.
摘要翻译：化合物半导体器件包括发射极层，与发射极层接触并由第一化合物半导体形成的基极层，与基极层接触并由具有较宽带隙的第二化合物半导体形成的集电极层比第一化合物半导体。在器件中，在集电极层和基极层之间的异质结界面处或在位于约10nm以下的集电极层的区域中形成杂质浓度高于集电极层的Δ掺杂层从与基层的异质结界面。

9. 发明授权

US06774455B2 Semiconductor device with a collector contact in a depressed well-region 有权
标题翻译：半导体器件在凹陷阱区域具有集电极接触
公开(公告)号：US06774455B2
公开(公告)日：2004-08-10
申请号：US10262206
申请日：2002-09-30
申请人： Jeffrey A. Babcock , Christoph Dirnecker , Angelo Pinto , Scott G. Balster , Michael Schober , Alfred Haeusler
发明人： Jeffrey A. Babcock , Christoph Dirnecker , Angelo Pinto , Scott G. Balster , Michael Schober , Alfred Haeusler
IPC分类号： H01L29737
CPC分类号： H01L29/66265 , H01L29/41708 , H01L29/66272 , H01L29/7317 , H01L29/732
摘要： A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. At least part of the active region is removed to form a shallow trench opening. A dielectric layer is formed proximate the active region at least partially within the shallow trench opening. At least part of the dielectric layer is removed to form a collector contact region. A collector contact may be formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.
摘要翻译：半导体器件的制造方法包括形成半导体衬底的掩埋层。在掩埋层的至少一部分附近形成有源区。移除活性区域的至少一部分以形成浅沟槽开口。在浅沟槽开口内至少部分地在有源区域附近形成电介质层。去除介电层的至少一部分以形成集电极接触区域。集电极触点可以在集电极接触区域形成。集电极触点可操作以电接触埋层。

10. 发明授权

US06600178B1 Heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管
公开(公告)号：US06600178B1
公开(公告)日：2003-07-29
申请号：US09599741
申请日：2000-06-23
申请人： Katsuyoshi Washio , Reiko Hayami , Hiromi Shimamoto , Masao Kondo , Katsuya Oda , Eiji Oue , Masamichi Tanabe
发明人： Katsuyoshi Washio , Reiko Hayami , Hiromi Shimamoto , Masao Kondo , Katsuya Oda , Eiji Oue , Masamichi Tanabe
IPC分类号： H01L29737
CPC分类号： H01L29/66242 , G02B6/4251 , G02B6/4274 , H01L29/7375 , H01L29/7378 , H03F3/45085 , H03F3/45089 , H03F2200/372 , H03F2203/45311 , H03F2203/45574 , H03F2203/45612 , H03F2203/45652 , H03F2203/45722
摘要： A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.
摘要翻译：提供了具有高可靠性和高增益的双极晶体管，并且特别适用于高速运行。双极晶体管以高精度工作，即使在集电极电压变化时也不会对集电极电流产生实质性的变化。与传统的集电极电流双极晶体管相比，它具有较小的变化，同时确保了高速性能和高增益。在一个示例中，基极区域中的带隙小于发射极和集电极区域中的带隙。带隙在与发射极区域的结点附近是恒定的，并且朝着与集电极区域的结点减小。单晶硅/锗通常用于基极区域。

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