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1. 发明公开

US20240162040A1 MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE WITH EFFICIENT EDGE STRUCTURE 审中-公开
公开(公告)号：US20240162040A1
公开(公告)日：2024-05-16
申请号：US18509043
申请日：2023-11-14
申请人： STMICROELECTRONICS S.r.l.
发明人： Edoardo ZANETTI , Simone RASCUNA' , Mario Giuseppe SAGGIO , Alfio GUARNERA , Leonardo FRAGAPANE , Cristina TRINGALI
IPC分类号： H01L21/04 , H01L21/285 , H01L29/06 , H01L29/16 , H01L29/66 , H01L29/78 , H01L29/872
CPC分类号： H01L21/046 , H01L21/0495 , H01L21/28537 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

2. 发明公开

US20230411158A1 METHOD FOR MANUFACTURING A SIC ELECTRONIC DEVICE WITH REDUCED HANDLING STEPS, AND SIC ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20230411158A1
公开(公告)日：2023-12-21
申请号：US18459273
申请日：2023-08-31
申请人： STMicroelectronics S.r.l.
发明人： Simone RASCUNA' , Paolo BADALA' , Anna BASSI , Mario Giuseppe SAGGIO , Giovanni FRANCO
IPC分类号： H01L21/04 , H01L29/16 , H01L29/45 , H01L29/47
CPC分类号： H01L21/0485 , H01L21/0495 , H01L29/1608 , H01L29/45 , H01L29/47
摘要： A method for manufacturing an electronic device based on SiC includes forming a structural layer of SiC on a front side of a substrate. The substrate has a back side that is opposite to the front side along a direction. Active regions of the electronic device are formed in the structure layer, and the active regions are configured to generate or conduct electric current during the use of the electronic device. A first electric terminal is formed on the structure layer, and an intermediate layer is formed at the back side of the substrate. The intermediate layer is heated by a LASER beam in order to generate local heating such as to favor the formation of an ohmic contact of Titanium compounds. A second electric terminal of the electronic device is formed on the intermediate layer.

3. 发明申请

US20180269335A1 SCHOTTKY BARRIER DIODE 审中-公开
公开(公告)号：US20180269335A1
公开(公告)日：2018-09-20
申请号：US15916813
申请日：2018-03-09
申请人： TOYODA GOSEI CO., LTD.
发明人： Kazuya HASEGAWA , Tohru Oka
IPC分类号： H01L29/872 , H01L29/66 , H01L29/47 , H01L21/04 , H01L29/20
CPC分类号： H01L29/872 , H01L21/0495 , H01L29/0657 , H01L29/2003 , H01L29/47 , H01L29/475 , H01L29/66143 , H01L29/66212
摘要： A Schottky barrier diode comprises a semiconductor layer configured to include a surface and a plurality of recesses that are recessed relative to the surface; and a Schottky electrode arranged to form a Schottky contact with the surface. When the semiconductor layer is viewed from a surface side thereof, the surface is arranged continuously, and distances on the surface between adjacent recesses are substantially identical. This configuration suppresses a photoresist from being left in any unintended portion.

4. 发明授权

US09799733B2 Semiconductor device having a junction portion contacting a schottky metal 有权
公开(公告)号：US09799733B2
公开(公告)日：2017-10-24
申请号：US14406106
申请日：2013-06-05
申请人： ROHM CO., LTD.
发明人： Yasuhiro Kawakami
IPC分类号： H01L29/16 , H01L29/66 , H01L21/04 , H01L29/872 , H01L29/47 , H01L29/417
CPC分类号： H01L29/1608 , H01L21/0495 , H01L29/417 , H01L29/47 , H01L29/66143 , H01L29/872 , H01L2224/02166 , H01L2224/04042 , H01L2224/05552 , H01L2224/05567 , H01L2924/00014 , H01L2924/12032 , H01L2924/00
摘要： A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal while the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm.

5. 发明申请

US20170221998A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20170221998A1
公开(公告)日：2017-08-03
申请号：US15307303
申请日：2014-12-15
申请人： Mitsubishi Electric Corporation
发明人： Kohei EBIHARA , Akihiro KOYAMA , Hidenori KOKETSU , Akemi NAGAE , Kotaro KAWAHARA , Hiroshi WATANABE , Kensuke TAGUCHI , Shiro HINO
IPC分类号： H01L29/16 , H01L29/78 , H01L29/06 , H01L29/66 , H01L29/872 , H01L29/36
CPC分类号： H01L29/1608 , H01L21/046 , H01L21/0495 , H01L29/06 , H01L29/0619 , H01L29/12 , H01L29/36 , H01L29/402 , H01L29/417 , H01L29/6606 , H01L29/66068 , H01L29/78 , H01L29/7823 , H01L29/872
摘要： An object of the present invention is to provide a silicon carbide semiconductor device with which the electric field at the time of switching is relaxed and the element withstand voltage can be enhanced. The distance between the outer peripheral end of a second surface electrode and the inner peripheral end of a field insulation film is smaller than the distance between an outer peripheral end of the second surface electrode and an inner peripheral end of the field insulation film in the case where the electric field strength applied to the outer peripheral lower end of the second surface electrode is calculated so as to become equal to the smallest dielectric breakdown strength among the dielectric breakdown strength of the field insulation film and the dielectric breakdown strength of the surface protective film at the time of switching when the value of dV/dt is greater than or equal to 10 kV/μs.

6. 发明申请

US20170170280A1 METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR ELEMENT 审中-公开
公开(公告)号：US20170170280A1
公开(公告)日：2017-06-15
申请号：US15442339
申请日：2017-02-24
申请人： SUMITOMO HEAVY INDUSTRIES, LTD.
发明人： Naoki Wakabayshi , Teruhisa Kawasaki
IPC分类号： H01L29/16 , H01L29/45 , H01L29/66 , H01L29/872 , H01L29/47 , H01L21/04 , H01L21/268
CPC分类号： H01L29/1608 , H01L21/0485 , H01L21/0495 , H01L21/268 , H01L29/0619 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/872
摘要： A method for manufacturing a semiconductor element, including forming a metal film, which contains at least one metal selected from the group consisting of titanium, tungsten, molybdenum, and chromium, on a first surface of a substrate formed of silicon carbide, and forming a metal silicide film by causing a silicide reaction within an interface between the substrate and the metal film by irradiating the metal film with a pulsed laser beam having a wavelength within a range of 330 nm to 370 nm.

7. 发明授权

US09559217B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US09559217B2
公开(公告)日：2017-01-31
申请号：US14892163
申请日：2014-04-02
申请人： Sumitomo Electric Industries, Ltd.
发明人： Keiji Wada , Kenji Kanbara
IPC分类号： H01L29/87 , H01L29/872 , H01L29/36 , H01L29/06 , H01L29/16 , H01L21/04 , H01L29/66 , H01L29/47
CPC分类号： H01L29/872 , H01L21/046 , H01L21/0495 , H01L29/0619 , H01L29/1608 , H01L29/36 , H01L29/47 , H01L29/6606
摘要： A silicon carbide semiconductor device includes a silicon carbide layer, an insulating layer, a Schottky electrode, and a reaction region. The silicon carbide layer includes a p type region in contact with a first main surface and an n type region in contact with the p type region and the first main surface. The insulating layer has a third main surface, a fourth main surface, and a side wall surface connecting the third main surface and the fourth main surface, and is in contact with the first main surface at the fourth main surface. The Schottky electrode is in contact with the first main surface and the side wall surface. The reaction region is in contact with the insulating layer, the Schottky electrode, and the p type region. The reaction region contains an element constituting the Schottky electrode, an element constituting the insulating layer, silicon, and carbon.
摘要翻译：碳化硅半导体器件包括碳化硅层，绝缘层，肖特基电极和反应区域。碳化硅层包括与第一主表面接触的p型区域和与p型区域和第一主表面接触的n型区域。绝缘层具有第三主表面，第四主表面和连接第三主表面和第四主表面的侧壁表面，并且在第四主表面处与第一主表面接触。肖特基电极与第一主表面和侧壁表面接触。反应区域与绝缘层，肖特基电极和p型区域接触。反应区域包含构成肖特基电极的元件，构成绝缘层的元素，硅和碳。

8. 发明申请

US20170018605A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20170018605A1
公开(公告)日：2017-01-19
申请号：US15279192
申请日：2016-09-28
申请人： HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
发明人： Kazuhiro MOCHIZUKI , Hidekatsu ONOSE , Norifumi KAMESHIRO , Natsuki YOKOYAMA
IPC分类号： H01L29/06 , H01L21/04 , H01L29/167 , H01L29/16 , H01L29/872
CPC分类号： H01L29/0619 , H01L21/046 , H01L21/0495 , H01L29/06 , H01L29/0615 , H01L29/1608 , H01L29/167 , H01L29/36 , H01L29/47 , H01L29/6606 , H01L29/8611 , H01L29/872
摘要： A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm−3 or higher and 6×1017 cm−3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm−3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm−3 or higher and 8×107 cm−3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm−3 or lower in a case of a junction barrier Schottky diode.
摘要翻译：提供了一种高可靠性的高耐压半导体器件。作为其手段，第一JTE区域中的杂质浓度设定为4.4×1017cm-3以上且6×1017cm-3以下，第二JTE区域的杂质浓度设定为2×1017cm-3 或者在肖特基二极管的情况下更低，并且第一JTE区域中的杂质浓度设定为6×1017cm-3以上且8×10 7 cm -3以下，并且设定第二JTE区域的杂质浓度在结势垒肖特基二极管的情况下为2×1017cm-3以下。

9. 发明授权

US09530647B2 Devices including ultra-short gates and methods of forming same 有权
标题翻译：包括超短门的装置及其形成方法
公开(公告)号：US09530647B2
公开(公告)日：2016-12-27
申请号：US14036799
申请日：2013-09-25
申请人： Cree, Inc.
发明人： Zoltan Ring , Dan Namishia
IPC分类号： H01L21/8234 , H01L21/04 , H01L21/285 , H01L21/443 , H01L21/311 , H01L29/423 , H01L21/28 , H01L29/66 , H01L29/20
CPC分类号： H01L21/049 , H01L21/0495 , H01L21/28114 , H01L21/28123 , H01L21/28587 , H01L21/31116 , H01L21/443 , H01L29/2003 , H01L29/42376 , H01L29/66553 , H01L29/6656 , H01L29/66621 , H01L29/66863
摘要： Provided are devices including ultra-short gates and methods of forming same. Methods include forming a first gate pattern on a semiconductor that includes a first recess having a first width. A dielectric spacer is formed on a sidewall of the first recess to define a second recess in the first recess that has a second width that is smaller than the first width. A gate having the second width is formed in the second recess.
摘要翻译：提供了包括超短栅的器件及其形成方法。方法包括在包括具有第一宽度的第一凹部的半导体上形成第一栅极图案。电介质间隔件形成在第一凹槽的侧壁上，以在第一凹槽中限定具有小于第一宽度的第二宽度的第二凹槽。具有第二宽度的门形成在第二凹部中。

10. 发明授权

US09496346B2 Silicon carbide device and a method for forming a silicon carbide device 有权
公开(公告)号：US09496346B2
公开(公告)日：2016-11-15
申请号：US14974553
申请日：2015-12-18
申请人： Infineon Technologies AG
发明人： Roland Rupp , Christian Hecht , Jens Konrath , Wolfgang Bergner , Hans-Joachim Schulze , Rudolf Elpelt
IPC分类号： H01L29/15 , H01L29/16 , H01L21/04 , H01L29/66 , H01L21/56 , H01L23/29 , H01L23/31 , H01L29/78 , H01L29/06 , H01L29/872
CPC分类号： H01L29/1608 , H01L21/045 , H01L21/046 , H01L21/047 , H01L21/0495 , H01L21/565 , H01L23/291 , H01L23/293 , H01L23/3135 , H01L23/3171 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/6606 , H01L29/66068 , H01L29/7811 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A silicon carbide device includes a silicon carbide substrate, an inorganic passivation layer structure and a molding material layer. The inorganic passivation layer structure laterally covers at least partly a main surface of the silicon carbide substrate and the molding material layer is arranged adjacent to the inorganic passivation layer structure.

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