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1. 发明授权

US06754106B1 Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory 有权
标题翻译：具有补偿非易失性存储器中的源极负载效应的各种负载电路的参考电池
公开(公告)号：US06754106B1
公开(公告)日：2004-06-22
申请号：US10245146
申请日：2002-09-16
申请人： Yider Wu , Jean Yang , Jiang Li
发明人： Yider Wu , Jean Yang , Jiang Li
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A load circuit for compensating for source side loading effects in a non-volatile memory. Specifically, embodiments of the present invention describe a reference cell that is coupled to a plurality of load circuits. At least one of the plurality of load circuits, an mth load circuit, comprises a select transistor coupled to m resistors that are coupled in series. The mth load circuit matches a source side loading effect of a corresponding mth memory cell located m memory cells away from a source line node on a source line coupling source regions in memory cells of a row of memory cells.
摘要翻译：用于补偿非易失性存储器中源侧负载效应的负载电路。具体地，本发明的实施例描述了耦合到多个负载电路的参考单元。多个负载电路中的至少一个负载电路包括耦合到串联耦合的m个电阻器的选择晶体管。第m个负载电路将位于m个存储单元的相应的第m个存储器单元的源极负载效应与源极线上的源极线节点耦合，该源极线耦合存储器单元的行的存储器单元中的源极区域。

2. 发明授权

US06628545B1 Memory circuit for suppressing bit line current leakage 有权
标题翻译：用于抑制位线电流泄漏的存储电路
公开(公告)号：US06628545B1
公开(公告)日：2003-09-30
申请号：US10306080
申请日：2002-11-26
申请人： Jiang Li , Yider Wu , Zhizheng Liu
发明人： Jiang Li , Yider Wu , Zhizheng Liu
IPC分类号： G11C1604
CPC分类号： G11C16/3404
摘要： A memory circuit employed in a memory device is disclosed. According to one embodiment, the memory circuit comprises a first memory cell and a second memory cell. The first memory cell has a drain terminal connected to a bit line, which is connected to a sensing circuit. The first memory cell also has a control gate connected to a word line. The second memory cell also has a drain terminal connected to the bit line. The second memory cell has its control gate coupled to ground. The memory circuit supplies a source voltage greater than a ground voltage to a source terminal of the first memory cell and to a source terminal of the second memory cell such that the gate-to-source voltage of the second memory cell is less than the threshold voltage of the second memory cell.
摘要翻译：公开了一种在存储器件中使用的存储器电路。根据一个实施例，存储器电路包括第一存储单元和第二存储单元。第一存储单元具有连接到位线的漏极端子，该位线连接到感测电路。第一存储单元还具有连接到字线的控制栅极。第二存储单元还具有连接到位线的漏极端子。第二存储单元的控制栅极接地。存储器电路将大于接地电压的源极电压提供给第一存储单元的源极端子和第二存储器单元的源极端子，使得第二存储器单元的栅极 - 源极电压小于阈值第二存储单元的电压。

3. 发明授权

US06331954B1 Determination of misalignment for floating gates near a gate stack bending point in array of flash memory cells 失效
标题翻译：确定闪存单元阵列中栅堆叠弯曲点附近浮动栅极的未对准
公开(公告)号：US06331954B1
公开(公告)日：2001-12-18
申请号：US09894777
申请日：2001-06-28
申请人： John J. Wang , Jiang Li , Yider Wu
发明人： John J. Wang , Jiang Li , Yider Wu
IPC分类号： G11C1634
CPC分类号： G11C29/50 , G11C16/04 , G11C29/24 , G11C2029/5002 , G11C2029/5006
摘要： For electrically determining the level of misalignment of floating gate structures closest to a gate stack bending point in an array of flash memory cells, a plurality of test flash memory cells are formed with each test flash memory cell having a respective floating gate structure designed to be disposed a respective displacement distance from a respective gate stack bending point. An erase operation is performed for each of the test flash memory cells by biasing the test flash memory cells with voltages from a plurality of voltage sources. Each of the test flash memory cells are then biased with test voltages from the plurality of voltage sources. A respective current meter then measures a respective amount of current flowing through each of the test flash memory cells when biased with the test voltages. The level of misalignment is determined depending on which of the test flash memory cells conducts a current level that is greater than a threshold current level when biased with the test voltages. The level of misalignment is approximately equal to a highest one of the respective displacement distance corresponding to one of the test flash memory cells that conducts a current level that is greater than the threshold current level.
摘要翻译：为了电气地确定最靠近闪速存储器单元阵列中的栅堆叠弯曲点的浮栅结构的未对准电平，形成多个测试闪存单元，每个测试闪速存储单元具有相应的浮栅结构，其设计为从相应的栅堆叠弯曲点设置相应的位移距离。通过利用来自多个电压源的电压偏置测试闪存单元，对每个测试闪存单元执行擦除操作。然后每个测试闪存单元被来自多个电压源的测试电压偏置。然后，相应的电流表随着测试电压的偏差测量流过每个测试闪存单元的相应电流量。根据测试闪速存储器单元中的哪一个导通当被测试电压偏置时大于阈值电流电平的电流电平来确定未对准电平。未对准的电平近似等于对应于传导大于阈值电流电平的电流电平的测试闪存单元之一的相应位移距离中的最高一个。

4. 发明授权

US06417082B1 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US06417082B1
公开(公告)日：2002-07-09
申请号：US09651684
申请日：2000-08-30
申请人： Yider Wu , Jean Yang , Hidehiko Shiraiwa , Mark E. Ramsbey
发明人： Yider Wu , Jean Yang , Hidehiko Shiraiwa , Mark E. Ramsbey
IPC分类号： H01L21425
CPC分类号： H01L21/28185 , H01L21/26506 , H01L21/26586
摘要： A process for making a semiconductor structure comprises implanting nitrogen through a layer comprising SiO2 into a substrate comprising Si, wherein the layer is on the substrate, and wherein the layer is from about 30 Å to about 300 Å thick.
摘要翻译：制造半导体结构的方法包括将氮通过包含SiO 2的层注入到包含Si的衬底中，其中该层在衬底上，并且其中该层为约30埃至约300埃。

5. 发明授权

US06403420B1 Nitrogen implant after bit-line formation for ONO flash memory devices 有权
标题翻译： ONO闪存器件位线形成后的氮注入
公开(公告)号：US06403420B1
公开(公告)日：2002-06-11
申请号：US09627664
申请日：2000-07-28
申请人： Jean Yang , Yider Wu , Mark Ramsbey , Yu Sun
发明人： Jean Yang , Yider Wu , Mark Ramsbey , Yu Sun
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/26506 , H01L21/28282 , H01L21/76202 , H01L27/115 , H01L29/66833
摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted after the ONO layer and junction areas have been formed. The entire semiconductor structure is heated to anneal out the nitrogen implant damage and to diffuse or drive the implanted nitrogen into the substrate and silicon oxide interface to form strong SiN bonds at that interface. By implanting nitrogen into the ONO stack, instead of a single silicon oxide layer as done conventionally, damage to the underlying silicon substrate is reduced. This results in better isolation between adjacent bit lines and suppresses leakages between adjacent bit lines.
摘要翻译：用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极第二层氧化硅。在ONO层和接合区域已经形成之后注入氮。整个半导体结构被加热以退出氮注入损伤，并将注入的氮扩散或驱动到衬底和氧化硅界面中，以在该界面处形成强的SiN键。通过将氮气注入到ONO堆叠中，代替如常规制造的单个氧化硅层，降低了底层硅衬底的损坏。这导致相邻位线之间更好的隔离并且抑制相邻位线之间的泄漏。

6. 发明授权

US06362051B1 Method of forming ONO flash memory devices using low energy nitrogen implantation 有权
标题翻译：使用低能氮注入形成ONO闪存器件的方法
公开(公告)号：US06362051B1
公开(公告)日：2002-03-26
申请号：US09648361
申请日：2000-08-25
申请人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
发明人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/26533 , H01L21/28282 , H01L21/3144 , H01L29/513 , H01L29/518
摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.
摘要翻译：用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极第二层氧化硅。氮以低于正常能级注入到第一氧化硅层中以减少对下面的半导体衬底的损伤量。在低能量氮注入之后，半导体结构被加热以退出注入损伤并将注入的氮扩散到衬底和氧化硅界面，以在该界面处形成SiN键。 SiN键是理想的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

7. 发明授权

US06395654B1 Method of forming ONO flash memory devices using rapid thermal oxidation 有权
标题翻译：使用快速热氧化形成ONO闪存器件的方法
公开(公告)号：US06395654B1
公开(公告)日：2002-05-28
申请号：US09648077
申请日：2000-08-25
申请人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
发明人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
IPC分类号： H01L21225
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and then the semiconductor structure is heated using a rapid thermal tool to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds are desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.
摘要翻译：用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极第二层氧化硅。将氮注入到第一层氧化硅中，然后使用快速热工具来加热半导体结构，以退出植入物损伤并将植入的氮扩散到衬底和氧化硅界面，以在该位置形成SiN键接口。 SiN键是期望的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

8. 发明授权

US10297607B2 Non-volatile memory having discrete isolation structure and SONOS memory cell, method of operating the same, and method of manufacturing the same 有权
公开(公告)号：US10297607B2
公开(公告)日：2019-05-21
申请号：US13615723
申请日：2012-09-14
申请人： Takao Akaogi , Yider Wu , Yi-Hsiu Chen
发明人： Takao Akaogi , Yider Wu , Yi-Hsiu Chen
IPC分类号： H01L27/11565 , H01L21/762 , H01L27/11568 , H01L21/8234
摘要： A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

9. 发明授权

US08012825B2 Method of manufacturing the double-implant nor flash memory structure 有权
标题翻译：制造双注入器或闪存结构的方法
公开(公告)号：US08012825B2
公开(公告)日：2011-09-06
申请号：US12350298
申请日：2009-01-08
申请人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
发明人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.
摘要翻译：在制造双注入NOR NOR闪存结构的方法中，执行磷离子注入工艺，使得在两个栅极结构之间的半导体衬底中形成P掺杂漏极区，以与高掺杂漏极（HDD ）区域和轻掺杂漏极（LDD）区域。因此，解决了HDD区域和LDD区域之间的连接处的电连接，并且解决了存储器中的载流子迁移率，同时解决了LDD区域的短沟道效应和穿通问题。

10. 发明申请

US20100227447A1 METHOD OF MANUFACTURING FLASH MEMORY DEVICE 审中-公开
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20100227447A1
公开(公告)日：2010-09-09
申请号：US12399124
申请日：2009-03-06
申请人： Hung-Wei Chen , Yider Wu
发明人： Hung-Wei Chen , Yider Wu
IPC分类号： H01L21/8234
CPC分类号： H01L27/11519 , H01L29/40114
摘要： A flash memory device manufacturing process includes the steps of providing a semiconductor substrate; forming two gate structures on the substrate; performing an ion implantation process to form two first source regions in the substrate at two lateral outer sides of the two gate structures; performing a further ion implantation process to form a first drain region in the substrate between the two gate structures; performing a pocket implantation process between the gate structures to form two doped regions in the substrate at two opposite sides of the first drain region; forming two facing L-shaped spacer walls between the two gate structures above the first drain region; performing an ion implantation process to form a second drain region beneath the first drain region, both of which having a steep junction profile compared to the first source regions; and forming a barrier plug above the first drain region.
摘要翻译：闪存器件制造方法包括以下步骤：提供半导体衬底; 在基板上形成两个栅极结构; 执行离子注入工艺以在两个栅极结构的两个侧向外侧处在衬底中形成两个第一源极区域; 执行另外的离子注入工艺以在所述两个栅极结构之间的所述衬底中形成第一漏极区; 在所述栅极结构之间执行凹穴注入工艺，以在所述衬底中在所述第一漏极区的两个相对侧形成两个掺杂区域; 在所述第一漏极区域之上的所述两个栅极结构之间形成两个面对的L形间隔壁; 执行离子注入工艺以在所述第一漏极区域下方形成第二漏极区域，所述第二漏极区域与所述第一源极区域相比具有陡峭的接合轮廓; 以及在所述第一漏极区域上方形成阻挡塞。

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