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    • 2. 发明授权
    • Memory circuit for suppressing bit line current leakage
    • 用于抑制位线电流泄漏的存储电路
    • US06628545B1
    • 2003-09-30
    • US10306080
    • 2002-11-26
    • Jiang LiYider WuZhizheng Liu
    • Jiang LiYider WuZhizheng Liu
    • G11C1604
    • G11C16/3404
    • A memory circuit employed in a memory device is disclosed. According to one embodiment, the memory circuit comprises a first memory cell and a second memory cell. The first memory cell has a drain terminal connected to a bit line, which is connected to a sensing circuit. The first memory cell also has a control gate connected to a word line. The second memory cell also has a drain terminal connected to the bit line. The second memory cell has its control gate coupled to ground. The memory circuit supplies a source voltage greater than a ground voltage to a source terminal of the first memory cell and to a source terminal of the second memory cell such that the gate-to-source voltage of the second memory cell is less than the threshold voltage of the second memory cell.
    • 公开了一种在存储器件中使用的存储器电路。 根据一个实施例,存储器电路包括第一存储单元和第二存储单元。 第一存储单元具有连接到位线的漏极端子,该位线连接到感测电路。 第一存储单元还具有连接到字线的控制栅极。 第二存储单元还具有连接到位线的漏极端子。 第二存储单元的控制栅极接地。 存储器电路将大于接地电压的源极电压提供给第一存储单元的源极端子和第二存储器单元的源极端子,使得第二存储器单元的栅极 - 源极电压小于阈值 第二存储单元的电压。
    • 3. 发明授权
    • Determination of misalignment for floating gates near a gate stack bending point in array of flash memory cells
    • 确定闪存单元阵列中栅堆叠弯曲点附近浮动栅极的未对准
    • US06331954B1
    • 2001-12-18
    • US09894777
    • 2001-06-28
    • John J. WangJiang LiYider Wu
    • John J. WangJiang LiYider Wu
    • G11C1634
    • G11C29/50G11C16/04G11C29/24G11C2029/5002G11C2029/5006
    • For electrically determining the level of misalignment of floating gate structures closest to a gate stack bending point in an array of flash memory cells, a plurality of test flash memory cells are formed with each test flash memory cell having a respective floating gate structure designed to be disposed a respective displacement distance from a respective gate stack bending point. An erase operation is performed for each of the test flash memory cells by biasing the test flash memory cells with voltages from a plurality of voltage sources. Each of the test flash memory cells are then biased with test voltages from the plurality of voltage sources. A respective current meter then measures a respective amount of current flowing through each of the test flash memory cells when biased with the test voltages. The level of misalignment is determined depending on which of the test flash memory cells conducts a current level that is greater than a threshold current level when biased with the test voltages. The level of misalignment is approximately equal to a highest one of the respective displacement distance corresponding to one of the test flash memory cells that conducts a current level that is greater than the threshold current level.
    • 为了电气地确定最靠近闪速存储器单元阵列中的栅堆叠弯曲点的浮栅结构的未对准电平,形成多个测试闪存单元,每个测试闪速存储单元具有相应的浮栅结构,其设计为 从相应的栅堆叠弯曲点设置相应的位移距离。 通过利用来自多个电压源的电压偏置测试闪存单元,对每个测试闪存单元执行擦除操作。 然后每个测试闪存单元被来自多个电压源的测试电压偏置。 然后,相应的电流表随着测试电压的偏差测量流过每个测试闪存单元的相应电流量。 根据测试闪速存储器单元中的哪一个导通当被测试电压偏置时大于阈值电流电平的电流电平来确定未对准电平。 未对准的电平近似等于对应于传导大于阈值电流电平的电流电平的测试闪存单元之一的相应位移距离中的最高一个。
    • 7. 发明授权
    • Network address translators (NAT) type detection techniques
    • 网络地址转换器(NAT)类型检测技术
    • US09160794B2
    • 2015-10-13
    • US12328296
    • 2008-12-04
    • Qingwei LinJiang LiJian-guang LouYusuo HuFan Li
    • Qingwei LinJiang LiJian-guang LouYusuo HuFan Li
    • G06F15/16H04L29/08H04L12/26H04L29/12H04L12/24H04L29/06
    • H04L67/104H04L29/12339H04L41/12H04L43/50H04L61/2503H04L69/28
    • Techniques described herein enable peers to determine each peer's NAT type much more efficiently and quickly than when compared with existing techniques. To do so, a peer simultaneously sends multiple test messages to a server. The peer then waits to either receive a response for each of the multiple test messages or may store an indication that no response has been received after a predetermined timeout period. The peer then analyzes the received responses and/or the stored timeout indications to determine the peer's NAT type or to determine that the peer is operating free from concealment by a NAT/firewall device. By simultaneously sending the multiple test messages, the peer may determine the NAT type within a maximum time defined by the predetermined timeout period or a roundtrip time period that is required for communication between the peer and the server. As such, the tools allow for efficient NAT-type detection.
    • 本文描述的技术使得对等体能够比与现有技术相比更有效和快速地确定每个对等体的NAT类型。 为此,对等体同时向服务器发送多个测试消息。 然后,对等体等待接收多个测试消息中的每一个的响应,或者可以存储在预定的超时时段之后没有接收到响应的指示。 对等体然后分析接收到的响应和/或存储的超时指示以确定对等体的NAT类型或者确定对等体正在从NAT /防火墙设备的隐藏中运行。 通过同时发送多个测试消息,对等体可以在由对等体和服务器之间的通信所需的预定超时时间段或往返时间周期限定的最大时间内确定NAT类型。 因此,这些工具允许有效的NAT类型检测。
    • 10. 发明授权
    • Charging connector
    • 充电连接器
    • US08475212B1
    • 2013-07-02
    • US13401760
    • 2012-02-21
    • Jiang LiMing-Han LinLi-Jun Xu
    • Jiang LiMing-Han LinLi-Jun Xu
    • H01R13/648
    • H01R24/38H01R4/023
    • A charging connector adapted for connecting between a mated connector and a cable includes an insulating housing, a terminal and a shielding shell surrounding the insulating housing. The insulating housing has a base body, and a protruding portion protruding upward from a top surface of the base body. The insulating housing defines a terminal groove. The terminal has a locating piece located on the top surface of the base body. A front of the locating piece defines a contact piece disposed in the terminal groove with a front thereof electrically contacting with the mated connector. A rear of the locating piece defines a soldering piece disposed to a rear of the insulating housing to be soldered with the cable. A side of the shielding shell defines a soldering plate disposed to one side of the insulating housing to be soldered with the cable.
    • 适于连接在配合连接器和电缆之间的充电连接器包括绝缘壳体,端子和围绕绝缘壳体的屏蔽壳。 绝缘壳体具有基体和从基体的顶面向上突出的突出部。 绝缘壳体限定端子槽。 端子具有位于基体顶面的定位片。 定位件的前部限定了设置在端子槽中的接触片,其前端与配合连接器电接触。 定位件的后部限定了设置在绝缘壳体的后部以与电缆焊接的焊件。 屏蔽壳的一侧限定了一个焊接板,该焊盘设置在待与电缆焊接的绝缘壳体的一侧。