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1. 发明申请

US20100227460A1 METHOD OF MANUFACTURING NOR FLASH MEMORY 审中-公开
标题翻译：制造或闪存存储器的方法
公开(公告)号：US20100227460A1
公开(公告)日：2010-09-09
申请号：US12399377
申请日：2009-03-06
申请人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
发明人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
IPC分类号： H01L21/4763
CPC分类号： H01L27/11521 , H01L21/76224
摘要： In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided.
摘要翻译：在制造NOR闪速存储器的方法中，当存储器件尺寸进一步减小时，省略在栅极结构的两个侧面处形成间隔物，并且两个栅极结构之间的间隔可以直接用介电间隔件或浅沟槽隔离（STI）层。因此，可以避免在栅极结构之间的极小空间中形成间隔物而造成存储器件制造难度增大的问题。该方法还能够省略形成硅化物层所需的自对准步骤。因此，也可以避免由于栅极结构之间的极小空间而导致的自对准难度。

2. 发明申请

US20100099262A1 METHOD OF MANUFACTURING NON-VOLATILE MEMORY CELL USING SELF-ALIGNED METAL SILICIDE 有权
标题翻译：使用自对准金属硅化物制造非挥发性记忆体的方法
公开(公告)号：US20100099262A1
公开(公告)日：2010-04-22
申请号：US12254022
申请日：2008-10-20
申请人： Yi-Hsiu Chen , Yung-Chung Lee , Yider Wu
发明人： Yi-Hsiu Chen , Yung-Chung Lee , Yider Wu
IPC分类号： H01L21/3105
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , Y10S438/976
摘要： In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.
摘要翻译：在制造非易失性存储单元的方法中，使用自对准金属硅化物代替常规钨金属层以形成多晶硅栅极，并且自对准金属硅化物用作多晶硅上的连接层门。通过使用自对准的金属硅化物来形成多晶硅栅极，可以节省在蚀刻工艺中使用掩模，从而能够简化制造工艺，从而降低制造成本。同时，可以避免由氧化的钨金属层引起的电阻偏移的问题。

3. 发明授权

US08012825B2 Method of manufacturing the double-implant nor flash memory structure 有权
标题翻译：制造双注入器或闪存结构的方法
公开(公告)号：US08012825B2
公开(公告)日：2011-09-06
申请号：US12350298
申请日：2009-01-08
申请人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
发明人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.
摘要翻译：在制造双注入NOR NOR闪存结构的方法中，执行磷离子注入工艺，使得在两个栅极结构之间的半导体衬底中形成P掺杂漏极区，以与高掺杂漏极（HDD ）区域和轻掺杂漏极（LDD）区域。因此，解决了HDD区域和LDD区域之间的连接处的电连接，并且解决了存储器中的载流子迁移率，同时解决了LDD区域的短沟道效应和穿通问题。

4. 发明申请

US20100230738A1 NOR FLASH MEMORY STRUCTURE WITH HIGHLY-DOPED DRAIN REGION AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有高排水区域的非闪存存储器结构及其制造方法
公开(公告)号：US20100230738A1
公开(公告)日：2010-09-16
申请号：US12400828
申请日：2009-03-10
申请人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
发明人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
IPC分类号： H01L29/788 , H01L21/336 , H01L29/00
CPC分类号： H01L27/11521 , H01L29/40114 , H01L29/42324
摘要： In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole.
摘要翻译：在制造NOR闪速存储器结构的方法中，执行高掺杂离子注入工艺以形成与轻掺杂漏极区重叠的高度掺杂的漏极区。因此，在用于形成接触孔的蚀刻工艺期间，闪速存储器结构可以具有减小的漏极结深度以改善短沟道效应，同时保护轻掺杂漏极区域不被穿孔。

5. 发明授权

US08158519B2 Method of manufacturing non-volatile memory cell using self-aligned metal silicide 有权
标题翻译：使用自对准金属硅化物制造非易失性存储单元的方法
公开(公告)号：US08158519B2
公开(公告)日：2012-04-17
申请号：US12254022
申请日：2008-10-20
申请人： Yi-Hsiu Chen , Yung-Chung Lee , Yider Wu
发明人： Yi-Hsiu Chen , Yung-Chung Lee , Yider Wu
IPC分类号： H01L21/84 , H01L21/00 , H01L21/8238 , H01L21/44
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , Y10S438/976
摘要： In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.
摘要翻译：在制造非易失性存储单元的方法中，使用自对准金属硅化物代替常规钨金属层以形成多晶硅栅极，并且自对准金属硅化物用作多晶硅上的连接层门。通过使用自对准的金属硅化物来形成多晶硅栅极，可以节省在蚀刻工艺中使用掩模，从而能够简化制造工艺，从而降低制造成本。同时，可以避免由氧化的钨金属层引起的电阻偏移的问题。

6. 发明申请

US20100171161A1 DOUBLE-IMPLANT NOR FLASH MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：双重印记或闪存存储器结构及其制造方法
公开(公告)号：US20100171161A1
公开(公告)日：2010-07-08
申请号：US12350298
申请日：2009-01-08
申请人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
发明人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
IPC分类号： H01L29/788 , H01L29/00 , H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.
摘要翻译：在制造双注入NOR NOR闪存结构的方法中，执行磷离子注入工艺，使得在两个栅极结构之间的半导体衬底中形成P掺杂漏极区，以与高掺杂漏极（HDD ）区域和轻掺杂漏极（LDD）区域。因此，解决了HDD区域和LDD区域之间的连接处的电连接，并且解决了存储器中的载流子迁移率，同时解决了LDD区域的短沟道效应和穿通问题。

7. 发明授权

US10297607B2 Non-volatile memory having discrete isolation structure and SONOS memory cell, method of operating the same, and method of manufacturing the same 有权
公开(公告)号：US10297607B2
公开(公告)日：2019-05-21
申请号：US13615723
申请日：2012-09-14
申请人： Takao Akaogi , Yider Wu , Yi-Hsiu Chen
发明人： Takao Akaogi , Yider Wu , Yi-Hsiu Chen
IPC分类号： H01L27/11565 , H01L21/762 , H01L27/11568 , H01L21/8234
摘要： A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

8. 发明申请

US20090086548A1 FLASH MEMORY 审中-公开
标题翻译：闪存
公开(公告)号：US20090086548A1
公开(公告)日：2009-04-02
申请号：US11866018
申请日：2007-10-02
申请人： Yider Wu , Yung-Chung Lee
发明人： Yider Wu , Yung-Chung Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： A flash memory applied in NAND and/or NOR flash memory has a silicon-oxide-nitride-oxide-silicon cell structure, uses channel-hot-electron injection as a write mechanism thereof to have a localized trapping characteristic, and uses hot-hole injection as an erase mechanism thereof. The flash memory uses an oxide-nitride-oxide structure to replace a floating gate, and thereby solves the problem of an entire leakage caused by a local leakage of the floating gate. The flash memory may be miniaturized without the problem of data mutual interference, and may be easily integrated into the CMOS process to largely reduce the manufacturing cost thereof. Meanwhile, the flash memory also enables faster program time and erase time.
摘要翻译：应用于NAND和/或NOR闪速存储器的闪速存储器具有氧化硅 - 氮化物 - 氧化物 - 硅电池结构，其通道 - 热电子注入作为其写入机制具有局部捕获特性，并且使用热孔注射作为其擦除机制。闪速存储器使用氧化物 - 氮化物 - 氧化物结构来代替浮动栅极，从而解决了浮栅的局部泄漏引起的整个泄漏的问题。闪存可以小型化而没有数据相互干扰的问题，并且可以容易地集成到CMOS工艺中以大大降低其制造成本。同时，闪存还可以实现更快的编程时间和擦除时间。

9. 发明申请

US20100227447A1 METHOD OF MANUFACTURING FLASH MEMORY DEVICE 审中-公开
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20100227447A1
公开(公告)日：2010-09-09
申请号：US12399124
申请日：2009-03-06
申请人： Hung-Wei Chen , Yider Wu
发明人： Hung-Wei Chen , Yider Wu
IPC分类号： H01L21/8234
CPC分类号： H01L27/11519 , H01L29/40114
摘要： A flash memory device manufacturing process includes the steps of providing a semiconductor substrate; forming two gate structures on the substrate; performing an ion implantation process to form two first source regions in the substrate at two lateral outer sides of the two gate structures; performing a further ion implantation process to form a first drain region in the substrate between the two gate structures; performing a pocket implantation process between the gate structures to form two doped regions in the substrate at two opposite sides of the first drain region; forming two facing L-shaped spacer walls between the two gate structures above the first drain region; performing an ion implantation process to form a second drain region beneath the first drain region, both of which having a steep junction profile compared to the first source regions; and forming a barrier plug above the first drain region.
摘要翻译：闪存器件制造方法包括以下步骤：提供半导体衬底; 在基板上形成两个栅极结构; 执行离子注入工艺以在两个栅极结构的两个侧向外侧处在衬底中形成两个第一源极区域; 执行另外的离子注入工艺以在所述两个栅极结构之间的所述衬底中形成第一漏极区; 在所述栅极结构之间执行凹穴注入工艺，以在所述衬底中在所述第一漏极区的两个相对侧形成两个掺杂区域; 在所述第一漏极区域之上的所述两个栅极结构之间形成两个面对的L形间隔壁; 执行离子注入工艺以在所述第一漏极区域下方形成第二漏极区域，所述第二漏极区域与所述第一源极区域相比具有陡峭的接合轮廓; 以及在所述第一漏极区域上方形成阻挡塞。

10. 发明申请

US20100197108A1 METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE STRUCTURE 有权
标题翻译：制造非易失性半导体存储器件结构的方法
公开(公告)号：US20100197108A1
公开(公告)日：2010-08-05
申请号：US12761460
申请日：2010-04-16
申请人： Yider Wu
发明人： Yider Wu
IPC分类号： H01L21/28 , H01L21/762
CPC分类号： H01L29/78 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.
摘要翻译：非易失性半导体制造方法包括以下步骤：制造在半导体衬底中分隔元件形成区域的元件隔离/绝缘膜; 通过第一栅极绝缘膜在半导体衬底上堆叠浮置栅极; 堆叠形成在浮置栅极上的第二栅极绝缘膜，并且通过第二栅极绝缘膜堆叠形成在浮置栅极上的控制栅极以及与控制栅极的自对准源极和漏极扩散区域。在通过在选择栅极区域中局部蚀刻场氧化物膜的同时堆叠浮栅的过程中，随后是形成在元件形成区域中的浮栅并选择栅极区域，然后进行化学机械抛光（CMP）工艺，浮动门和选择门同时形成。因此，当存储单元小型化时，本发明允许该过程简单并减少缺陷密度。

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