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1. 发明授权

US06395654B1 Method of forming ONO flash memory devices using rapid thermal oxidation 有权
标题翻译：使用快速热氧化形成ONO闪存器件的方法
公开(公告)号：US06395654B1
公开(公告)日：2002-05-28
申请号：US09648077
申请日：2000-08-25
申请人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
发明人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
IPC分类号： H01L21225
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and then the semiconductor structure is heated using a rapid thermal tool to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds are desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.
摘要翻译：用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极第二层氧化硅。将氮注入到第一层氧化硅中，然后使用快速热工具来加热半导体结构，以退出植入物损伤并将植入的氮扩散到衬底和氧化硅界面，以在该位置形成SiN键接口。 SiN键是期望的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

2. 发明授权

US06362051B1 Method of forming ONO flash memory devices using low energy nitrogen implantation 有权
标题翻译：使用低能氮注入形成ONO闪存器件的方法
公开(公告)号：US06362051B1
公开(公告)日：2002-03-26
申请号：US09648361
申请日：2000-08-25
申请人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
发明人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/26533 , H01L21/28282 , H01L21/3144 , H01L29/513 , H01L29/518
摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.
摘要翻译：用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极第二层氧化硅。氮以低于正常能级注入到第一氧化硅层中以减少对下面的半导体衬底的损伤量。在低能量氮注入之后，半导体结构被加热以退出注入损伤并将注入的氮扩散到衬底和氧化硅界面，以在该界面处形成SiN键。 SiN键是理想的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

3. 发明授权

US06417082B1 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US06417082B1
公开(公告)日：2002-07-09
申请号：US09651684
申请日：2000-08-30
申请人： Yider Wu , Jean Yang , Hidehiko Shiraiwa , Mark E. Ramsbey
发明人： Yider Wu , Jean Yang , Hidehiko Shiraiwa , Mark E. Ramsbey
IPC分类号： H01L21425
CPC分类号： H01L21/28185 , H01L21/26506 , H01L21/26586
摘要： A process for making a semiconductor structure comprises implanting nitrogen through a layer comprising SiO2 into a substrate comprising Si, wherein the layer is on the substrate, and wherein the layer is from about 30 Å to about 300 Å thick.
摘要翻译：制造半导体结构的方法包括将氮通过包含SiO 2的层注入到包含Si的衬底中，其中该层在衬底上，并且其中该层为约30埃至约300埃。

4. 发明授权

US06403420B1 Nitrogen implant after bit-line formation for ONO flash memory devices 有权
标题翻译： ONO闪存器件位线形成后的氮注入
公开(公告)号：US06403420B1
公开(公告)日：2002-06-11
申请号：US09627664
申请日：2000-07-28
申请人： Jean Yang , Yider Wu , Mark Ramsbey , Yu Sun
发明人： Jean Yang , Yider Wu , Mark Ramsbey , Yu Sun
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/26506 , H01L21/28282 , H01L21/76202 , H01L27/115 , H01L29/66833
摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted after the ONO layer and junction areas have been formed. The entire semiconductor structure is heated to anneal out the nitrogen implant damage and to diffuse or drive the implanted nitrogen into the substrate and silicon oxide interface to form strong SiN bonds at that interface. By implanting nitrogen into the ONO stack, instead of a single silicon oxide layer as done conventionally, damage to the underlying silicon substrate is reduced. This results in better isolation between adjacent bit lines and suppresses leakages between adjacent bit lines.
摘要翻译：用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极第二层氧化硅。在ONO层和接合区域已经形成之后注入氮。整个半导体结构被加热以退出氮注入损伤，并将注入的氮扩散或驱动到衬底和氧化硅界面中，以在该界面处形成强的SiN键。通过将氮气注入到ONO堆叠中，代替如常规制造的单个氧化硅层，降低了底层硅衬底的损坏。这导致相邻位线之间更好的隔离并且抑制相邻位线之间的泄漏。

5. 发明授权

US06754106B1 Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory 有权
标题翻译：具有补偿非易失性存储器中的源极负载效应的各种负载电路的参考电池
公开(公告)号：US06754106B1
公开(公告)日：2004-06-22
申请号：US10245146
申请日：2002-09-16
申请人： Yider Wu , Jean Yang , Jiang Li
发明人： Yider Wu , Jean Yang , Jiang Li
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A load circuit for compensating for source side loading effects in a non-volatile memory. Specifically, embodiments of the present invention describe a reference cell that is coupled to a plurality of load circuits. At least one of the plurality of load circuits, an mth load circuit, comprises a select transistor coupled to m resistors that are coupled in series. The mth load circuit matches a source side loading effect of a corresponding mth memory cell located m memory cells away from a source line node on a source line coupling source regions in memory cells of a row of memory cells.
摘要翻译：用于补偿非易失性存储器中源侧负载效应的负载电路。具体地，本发明的实施例描述了耦合到多个负载电路的参考单元。多个负载电路中的至少一个负载电路包括耦合到串联耦合的m个电阻器的选择晶体管。第m个负载电路将位于m个存储单元的相应的第m个存储器单元的源极负载效应与源极线上的源极线节点耦合，该源极线耦合存储器单元的行的存储器单元中的源极区域。

6. 发明申请

US20070093042A1 Bit line implant 有权
标题翻译：位线植入
公开(公告)号：US20070093042A1
公开(公告)日：2007-04-26
申请号：US11254769
申请日：2005-10-21
申请人： Angela Hui , Jean Yang , Yu Sun , Mark Ramsbey , Weidong Qian
发明人： Angela Hui , Jean Yang , Yu Sun , Mark Ramsbey , Weidong Qian
IPC分类号： H01L21/04
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.
摘要翻译：公开了一种用于执行位线植入的方法。该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。该组结构的每个结构包括多晶硅部分和硬掩模部分。该组结构的第一结构与该组结构的第二结构分开小于100纳米。该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。

7. 发明授权

US07432178B2 Bit line implant 有权
标题翻译：位线植入
公开(公告)号：US07432178B2
公开(公告)日：2008-10-07
申请号：US11254769
申请日：2005-10-21
申请人： Angela T. Hui , Jean Yang , Yu Sun , Mark T. Ramsbey , Weidong Qian
发明人： Angela T. Hui , Jean Yang , Yu Sun , Mark T. Ramsbey , Weidong Qian
IPC分类号： H01L21/04
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.
摘要翻译：公开了一种用于执行位线植入的方法。该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。该组结构的每个结构包括多晶硅部分和硬掩模部分。该组结构的第一结构与该组结构的第二结构分开小于100纳米。该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。

8. 外观设计

USD460249S1 Shoe bottom 失效
公开(公告)号：USD460249S1
公开(公告)日：2002-07-16
申请号：US29142235
申请日：2001-05-21
申请人： Jean Yang
设计人： Jean Yang

9. 发明授权

US06277661B1 Method for detecting sloped contact holes using a critical-dimension waveform 有权
标题翻译：使用临界尺寸波形检测倾斜接触孔的方法
公开(公告)号：US06277661B1
公开(公告)日：2001-08-21
申请号：US09677955
申请日：2000-10-02
申请人： Jean Yang , Ian Dudley , Khoi Phan
发明人： Jean Yang , Ian Dudley , Khoi Phan
IPC分类号： H01L2166
CPC分类号： H01L22/26 , H01L22/12
摘要： A method for contact hole formation and inspection during integrated circuit fabrication is disclosed. The method includes defining tolerances for one or more contact hole formation processes, and then performing the formation processes to create at least one contact hole. After at least one of the formation processes is performed, a waveform is generated for the contact hole. A critical dimension (CD) and an edge width value are then generated for the contact hole from the waveform. The CD and the edge width value are then compared to the tolerances to detect and correct variations in the formation process. In a further aspect of the present invention, the edge width is compared to a predetermined limit to automatically detect contact holes having sloped sidewalls.
摘要翻译：公开了一种在集成电路制造期间接触孔形成和检查的方法。该方法包括确定一个或多个接触孔形成过程的公差，然后执行形成过程以产生至少一个接触孔。在执行至少一个形成处理之后，产生用于接触孔的波形。然后为波形的接触孔产生临界尺寸（CD）和边缘宽度值。然后将CD和边缘宽度值与公差进行比较，以检测和纠正形成过程中的变化。在本发明的另一方面，将边缘宽度与预定极限进行比较，以自动检测具有倾斜侧壁的接触孔。

10. 发明授权

US07998846B2 3-D integrated circuit system and method 有权
标题翻译： 3-D集成电路系统及方法
公开(公告)号：US07998846B2
公开(公告)日：2011-08-16
申请号：US12209478
申请日：2008-09-12
申请人： Eunha Kim , Jeremy Wahl , Shenqing Fang , YouSeok Suh , Kuo-Tung Chang , Yi Ma , Rinji Sugino , Jean Yang
发明人： Eunha Kim , Jeremy Wahl , Shenqing Fang , YouSeok Suh , Kuo-Tung Chang , Yi Ma , Rinji Sugino , Jean Yang
IPC分类号： H01L21/263
CPC分类号： H01L21/02675 , H01L21/02592 , H01L21/02691
摘要： A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.
摘要翻译：提出了半导体制造系统和方法。三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。

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