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1. 发明授权

US5787190A Method and apparatus for pattern recognition of wafer test bins 失效
标题翻译：晶圆测试箱的模式识别方法和装置
公开(公告)号：US5787190A
公开(公告)日：1998-07-28
申请号：US884316
申请日：1997-06-27
申请人： Yeng-Kaung Peng , Siu-May Ho , Ying Shiau
发明人： Yeng-Kaung Peng , Siu-May Ho , Ying Shiau
IPC分类号： H01L21/66
CPC分类号： H01L22/20
摘要： An automated system and procedure processes wafer test bin data of semiconductor wafers to formulate a fault pattern at statistically significant levels. A processor such as a neural engine or neural network collects wafer test bin results to generate a N/N wafer map to be correlated with wafer maps produced from a wafer electrical test, a wafer level reliability test, and an in-line defect analysis. A N/N wafer map generated by the processor is cross-checked with a wafer map generated from another semiconductor tester to formulate possible overlap fault patterns. The confirmed fault patterns are further analyzed by performing failure analysis to find the root cause of fault patterns. A report containing fault patterns and the root cause for fault patterns is sent back to a fab for making adjustment to the fabrication process to increase the overall yield of the future batch of semiconductor wafers. The report is also stored in a pattern database to serve as a library for future reference of previously recognized fault patterns, thereby to bypass the need to perform a failure analysis for matching fault patterns.
摘要翻译：自动化系统和程序处理半导体晶片的晶圆测试箱数据，以制定统计学显着水平的故障模式。诸如神经引擎或神经网络的处理器收集晶片测试箱结果以产生N / N晶片图，以与从晶片电测试，晶片级可靠性测试和在线缺陷分析产生的晶片图相关联。由处理器产生的N / N晶片图与从另一半导体测试仪生成的晶片图进行交叉检查，以制定可能的重叠故障模式。通过执行故障分析，找出故障模式的根本原因进一步分析确认的故障模式。包含故障模式和故障模式的根本原因的报告被发送回制造厂，以调整制造工艺以提高未来批次的半导体晶片的总体产量。报告也存储在模式数据库中，用作库以供以前识别的故障模式的参考，从而绕过对故障模式匹配进行故障分析的需要。

2. 发明授权

US5598341A Real-time in-line defect disposition and yield forecasting system 失效
标题翻译：实时在线缺陷处置和收益预测系统
公开(公告)号：US5598341A
公开(公告)日：1997-01-28
申请号：US401490
申请日：1995-03-10
申请人： Zhi-Min Ling , Thao Vo , Siu-May Ho , Ying Shiau , Yeng-Kaung Peng , Yung-Tao Lin
发明人： Zhi-Min Ling , Thao Vo , Siu-May Ho , Ying Shiau , Yeng-Kaung Peng , Yung-Tao Lin
IPC分类号： G01N21/95 , G03F7/20 , H01L21/00 , H01L21/66 , G06F19/00
CPC分类号： H01L21/67288 , G01N21/9501 , G03F7/705 , G03F7/7065 , H01L21/67276 , H01L22/20
摘要： A real-time in-line defect disposition and yield forecasting system for a semiconductor wafer having layer containing devices includes an in-line fabrication inspection tool, a design review station, and a yield management station. The in-line fabrication inspection tool inspects at least two layers of the semiconductor wafer and produces first information including particle size, particle location and number of particles introduced therein for each of these layers. The design review station inspects the layers of the semiconductor wafer and produces second information including layouts of each of the layers. The yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station retrieves the first information and the second information from the in-line fabrication inspection tool and from the design review station. The yield management station determines at least one of a number of killer defects for the devices in each of the layers or a defect sensitive area index for each of the layers using the first and second information. The yield management station also determines a priority for analyzing each of the at least two layers responsive to at least one of the number of killer defects and the defect sensitive area index for each of the layers.
摘要翻译：具有层包含装置的半导体晶片的实时在线缺陷布置和产量预测系统包括在线制造检查工具，设计审查站和产量管理站。在线制造检查工具检查半导体晶片的至少两层，并且产生包括其中为每个这些层引入的颗粒尺寸，颗粒位置和颗粒数量的第一信息。设计检查站检查半导体晶片的层，并产生包括每个层的布局的第二信息。产量管理站可操作地连接到在线制造检查工具和设计审查站。产量管理站从设计检查站检索来自在线制造检验工具的第一信息和第二信息。收益管理站使用第一和第二信息确定每个层中的设备的多个杀手缺陷中的至少一个或每个层的缺陷敏感区域索引。收益管理站还根据每个层的凶手缺陷数量和缺陷敏感区域索引中的至少一个来确定分析至少两个层中的每一个的优先级。

3. 发明授权

US6028994A Method for predicting performance of microelectronic device based on electrical parameter test data using computer model 失效
标题翻译：基于电参数测试数据使用计算机模型预测微电子器件性能的方法
公开(公告)号：US6028994A
公开(公告)日：2000-02-22
申请号：US73619
申请日：1998-05-06
申请人： Yeng-Kaung Peng , Chern-Jiann Lee , Siu-May Ho
发明人： Yeng-Kaung Peng , Chern-Jiann Lee , Siu-May Ho
IPC分类号： G01R31/30 , H01L21/66 , G06F9/455
CPC分类号： H01L22/20 , G01R31/30
摘要： Electrical parameter testing and performance testing are performed on a plurality of microelectronic devices to obtain parametric values and performance values respectively. The parametric values are applied as inputs to a computer program such as a back propagation neural network engine which generates a performance prediction model by self-learning that implements a function relating the performance values to the parametric values. The model is used to predict the performance of devices being fabricated by performing electrical parameter testing on these devices and applying the resulting parametric values to the model as inputs to produce predicted performance values as outputs. The model can be configured to produce predicted performance values as percentages of devices having speed or other parameters in predetermined respective ranges. The model can be further configured to produce predicted performance values as percentages of devices having different types of defects. The model can be improved by self-learning using additional test values. The model can also be used to identify parameters which result in low performance and improve devices being fabricated by adjusting the corresponding process parameters.
摘要翻译：在多个微电子器件上执行电参数测试和性能测试，以分别获得参数值和性能值。将参数值作为输入应用于计算机程序，例如反向传播神经网络引擎，其通过自学习产生性能预测模型，该模型实现与性能值相关的参数值。该模型用于通过对这些器件执行电气参数测试来预测正在制造的器件的性能，并将所得到的参数值作为输入应用到模型中，以产生预测的性能值作为输出。该模型可以被配置为产生预测的性能值，作为具有预定相应范围内的速度或其他参数的设备的百分比。该模型可进一步配置为产生具有不同类型缺陷的设备的百分比的预测性能值。该模型可以通过使用附加测试值的自学习来改进。该模型还可用于识别导致低性能的参数，并通过调整相应的过程参数来改进制造的器件。

4. 发明授权

US5822717A Method and apparatus for automated wafer level testing and reliability data analysis 失效
标题翻译：自动化晶圆级测试和可靠性数据分析的方法和设备
公开(公告)号：US5822717A
公开(公告)日：1998-10-13
申请号：US509362
申请日：1995-07-31
申请人： Jerry Tsiang , Mikkel Lantz , Yeng-Kaung Peng , Ying Shiau
发明人： Jerry Tsiang , Mikkel Lantz , Yeng-Kaung Peng , Ying Shiau
IPC分类号： G01R31/28 , G01R31/319 , H01L21/66 , G01R17/50
CPC分类号： G01R31/31903 , G01R31/2831 , G01R31/2834 , G01R31/2851
摘要： Methods and apparatus are disclosed for testing integrated circuits at the wafer level and for integrating test results, calculation of lifetimes and generation of trend charts in a common database following testing. A wafer tester controller is supplemented with additional hardware and software to avoid data transfer errors and facilitate processing and storage of test results. The data base is available over a network to all areas of an organization.
摘要翻译：公开了用于在晶片级测试集成电路并且用于在测试之后的通用数据库中集成测试结果，寿命计算和趋势图的生成的方法和装置。晶圆测试仪控制器补充有额外的硬件和软件，以避免数据传输错误，便于处理和存储测试结果。数据库可通过网络提供给组织的所有区域。

5. 发明授权

US5561293A Method of failure analysis with CAD layout navigation and FIB/SEM inspection 失效
标题翻译： CAD布局导航和FIB / SEM检查故障分析方法
公开(公告)号：US5561293A
公开(公告)日：1996-10-01
申请号：US425110
申请日：1995-04-20
申请人： Yeng-Kaung Peng , Thao H. Vo , Paul M. Wong
发明人： Yeng-Kaung Peng , Thao H. Vo , Paul M. Wong
IPC分类号： H01J37/30 , H01L21/66 , H01J37/00
CPC分类号： H01J37/3005 , H01L22/20 , H01J2237/24592 , H01J2237/2817 , H01J2237/30411 , H01L22/12
摘要： A method of analyzing a failure of a sample, such as a wafer or a package unit made from a die sliced from the wafer, uses a computer aided design (CAD) tool in conjunction with a dual beam scanner and reverse engineering to improve the yield of the product. The computer aided design tool provides navigation to a location of interest over a layout of a wafer sample which has failed a test. The location of interest of the sample is then inspected using the dual beam scanner. The inspection may be made with either a focused ion beam scan or with a scanning electron microscope scan to provide different types of scan images and information. After inspection, a reverse engineering process (stripping back) is performed on the sample and the sample is inspected again to determine the cause of the failure of the sample. Once the cause of the failure is determined, the manufacturing process can be changed to improve the yield of the wafers.
摘要翻译：分析样品故障的方法，例如晶片或由晶片切片的芯片制成的封装单元，使用计算机辅助设计（CAD）工具结合双光束扫描仪和逆向工程来提高产量的产品。计算机辅助设计工具提供导航到在测试失败的晶片样本的布局上感兴趣的位置。然后使用双光束扫描仪检查样品的感兴趣位置。可以用聚焦离子束扫描或扫描电子显微镜扫描进行检查，以提供不同类型的扫描图像和信息。在检查后，对样品进行逆向工程（剥离），并再次检查样品以确定样品失效的原因。一旦确定了故障的原因，可以改变制造过程以提高晶片的产量。

6. 发明授权

US5886909A Defect diagnosis using simulation for IC yield improvement 失效
标题翻译：缺陷诊断使用模拟IC产量提高
公开(公告)号：US5886909A
公开(公告)日：1999-03-23
申请号：US994960
申请日：1997-12-19
申请人： Linda Milor , Yeng-Kaung Peng , Khoi Anh Phan , David Steele
发明人： Linda Milor , Yeng-Kaung Peng , Khoi Anh Phan , David Steele
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： H01L22/20
摘要： Defects in integrated circuit wafers (10) are often difficult to diagnose, because patterned wafer inspections can only be done after certain wafer processing steps. Defect simulation is used to understand the relation between defects in the wafer (10) and the resulting wafer profiles. Defects such as particles (50) and bubbles (22) in the photoresist (28), for example, translate into a wide variety of defective profiles. Knowledge of the relation between defects and the defect profiles can assist in yield improvement efforts, since defects may be diagnosed by comparing simulated and observed defect profiles. From the simulated defect profiles, methods can be adapted to fix or correct observed defects.
摘要翻译：集成电路晶片（10）中的缺陷通常难以诊断，因为图案化晶片检查只能在某些晶片处理步骤之后进行。使用缺陷模拟来了解晶片（10）中的缺陷与所得晶片轮廓之间的关系。例如，光致抗蚀剂（28）中的诸如颗粒（50）和气泡（22）的缺陷转化成各种缺陷型材。了解缺陷和缺陷轮廓之间的关系可以帮助改善产量，因为可以通过比较模拟和观察到的缺陷轮廓来诊断缺陷。根据模拟的缺陷轮廓，可以调整方法来修正或纠正观察到的缺陷。

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