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1. 发明授权

US5787190A Method and apparatus for pattern recognition of wafer test bins 失效
标题翻译：晶圆测试箱的模式识别方法和装置
公开(公告)号：US5787190A
公开(公告)日：1998-07-28
申请号：US884316
申请日：1997-06-27
申请人： Yeng-Kaung Peng , Siu-May Ho , Ying Shiau
发明人： Yeng-Kaung Peng , Siu-May Ho , Ying Shiau
IPC分类号： H01L21/66
CPC分类号： H01L22/20
摘要： An automated system and procedure processes wafer test bin data of semiconductor wafers to formulate a fault pattern at statistically significant levels. A processor such as a neural engine or neural network collects wafer test bin results to generate a N/N wafer map to be correlated with wafer maps produced from a wafer electrical test, a wafer level reliability test, and an in-line defect analysis. A N/N wafer map generated by the processor is cross-checked with a wafer map generated from another semiconductor tester to formulate possible overlap fault patterns. The confirmed fault patterns are further analyzed by performing failure analysis to find the root cause of fault patterns. A report containing fault patterns and the root cause for fault patterns is sent back to a fab for making adjustment to the fabrication process to increase the overall yield of the future batch of semiconductor wafers. The report is also stored in a pattern database to serve as a library for future reference of previously recognized fault patterns, thereby to bypass the need to perform a failure analysis for matching fault patterns.
摘要翻译：自动化系统和程序处理半导体晶片的晶圆测试箱数据，以制定统计学显着水平的故障模式。诸如神经引擎或神经网络的处理器收集晶片测试箱结果以产生N / N晶片图，以与从晶片电测试，晶片级可靠性测试和在线缺陷分析产生的晶片图相关联。由处理器产生的N / N晶片图与从另一半导体测试仪生成的晶片图进行交叉检查，以制定可能的重叠故障模式。通过执行故障分析，找出故障模式的根本原因进一步分析确认的故障模式。包含故障模式和故障模式的根本原因的报告被发送回制造厂，以调整制造工艺以提高未来批次的半导体晶片的总体产量。报告也存储在模式数据库中，用作库以供以前识别的故障模式的参考，从而绕过对故障模式匹配进行故障分析的需要。

2. 发明授权

US5598341A Real-time in-line defect disposition and yield forecasting system 失效
标题翻译：实时在线缺陷处置和收益预测系统
公开(公告)号：US5598341A
公开(公告)日：1997-01-28
申请号：US401490
申请日：1995-03-10
申请人： Zhi-Min Ling , Thao Vo , Siu-May Ho , Ying Shiau , Yeng-Kaung Peng , Yung-Tao Lin
发明人： Zhi-Min Ling , Thao Vo , Siu-May Ho , Ying Shiau , Yeng-Kaung Peng , Yung-Tao Lin
IPC分类号： G01N21/95 , G03F7/20 , H01L21/00 , H01L21/66 , G06F19/00
CPC分类号： H01L21/67288 , G01N21/9501 , G03F7/705 , G03F7/7065 , H01L21/67276 , H01L22/20
摘要： A real-time in-line defect disposition and yield forecasting system for a semiconductor wafer having layer containing devices includes an in-line fabrication inspection tool, a design review station, and a yield management station. The in-line fabrication inspection tool inspects at least two layers of the semiconductor wafer and produces first information including particle size, particle location and number of particles introduced therein for each of these layers. The design review station inspects the layers of the semiconductor wafer and produces second information including layouts of each of the layers. The yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station retrieves the first information and the second information from the in-line fabrication inspection tool and from the design review station. The yield management station determines at least one of a number of killer defects for the devices in each of the layers or a defect sensitive area index for each of the layers using the first and second information. The yield management station also determines a priority for analyzing each of the at least two layers responsive to at least one of the number of killer defects and the defect sensitive area index for each of the layers.
摘要翻译：具有层包含装置的半导体晶片的实时在线缺陷布置和产量预测系统包括在线制造检查工具，设计审查站和产量管理站。在线制造检查工具检查半导体晶片的至少两层，并且产生包括其中为每个这些层引入的颗粒尺寸，颗粒位置和颗粒数量的第一信息。设计检查站检查半导体晶片的层，并产生包括每个层的布局的第二信息。产量管理站可操作地连接到在线制造检查工具和设计审查站。产量管理站从设计检查站检索来自在线制造检验工具的第一信息和第二信息。收益管理站使用第一和第二信息确定每个层中的设备的多个杀手缺陷中的至少一个或每个层的缺陷敏感区域索引。收益管理站还根据每个层的凶手缺陷数量和缺陷敏感区域索引中的至少一个来确定分析至少两个层中的每一个的优先级。

3. 发明授权

US5822717A Method and apparatus for automated wafer level testing and reliability data analysis 失效
标题翻译：自动化晶圆级测试和可靠性数据分析的方法和设备
公开(公告)号：US5822717A
公开(公告)日：1998-10-13
申请号：US509362
申请日：1995-07-31
申请人： Jerry Tsiang , Mikkel Lantz , Yeng-Kaung Peng , Ying Shiau
发明人： Jerry Tsiang , Mikkel Lantz , Yeng-Kaung Peng , Ying Shiau
IPC分类号： G01R31/28 , G01R31/319 , H01L21/66 , G01R17/50
CPC分类号： G01R31/31903 , G01R31/2831 , G01R31/2834 , G01R31/2851
摘要： Methods and apparatus are disclosed for testing integrated circuits at the wafer level and for integrating test results, calculation of lifetimes and generation of trend charts in a common database following testing. A wafer tester controller is supplemented with additional hardware and software to avoid data transfer errors and facilitate processing and storage of test results. The data base is available over a network to all areas of an organization.
摘要翻译：公开了用于在晶片级测试集成电路并且用于在测试之后的通用数据库中集成测试结果，寿命计算和趋势图的生成的方法和装置。晶圆测试仪控制器补充有额外的硬件和软件，以避免数据传输错误，便于处理和存储测试结果。数据库可通过网络提供给组织的所有区域。

4. 发明授权

US5930138A Arrangement and method for detecting sequential processing effects in manufacturing using predetermined sequences within runs 失效
标题翻译：用于使用运行中的预定序列来检测制造中的顺序处理效果的布置和方法
公开(公告)号：US5930138A
公开(公告)日：1999-07-27
申请号：US926487
申请日：1997-09-10
申请人： Yung-Tao Lin , Zhi-Min Ling , James Pak , Ying Shiau
发明人： Yung-Tao Lin , Zhi-Min Ling , James Pak , Ying Shiau
IPC分类号： H01L21/66 , G06F19/00 , G06G7/64 , G06G7/66
CPC分类号： H01L22/20 , Y10S148/162
摘要： An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data. These steps are repeated for subsequent sets of the products, so that although the specified processing sequence is different for each of the individual process steps for a set of products, the same processing sequences for the individual processing steps are used for subsequent sets of the products to be manufactured. Since the processing sequences are not randomized from set to set and do not have to be provided to a database, the amounts of interfacing and disk storage needed are greatly reduced.
摘要翻译：用于检测对在制造过程中制造的产品的顺序处理影响的布置和方法，以在制造过程中的第一处理步骤的第一指定处理顺序中对第一组产品进行订购。为了防止在一个处理步骤中产生的任何位置趋势被转移到下一个处理步骤中，将第一组产品重新排列成制造过程中第二个处理步骤的第二个不同的指定处理顺序。提取关于第一组产品对处理步骤的响应的数据。提取的数据与第一和第二处理序列相关，并且对相关的提取数据进行数据分析。对于随后的产品组重复这些步骤，使得尽管对于一组产品的各个处理步骤的指定处理顺序是不同的，但是用于各个处理步骤的相同处理顺序用于随后的产品集合被制造。由于处理序列不是从集合中随机化设置的，并且不必提供给数据库，因此大大减少了所需的接口和磁盘存储量。

5. 发明授权

US5821765A Apparatus for detecting defect sizes in polysilicon and source-drain semiconductor devices and method for making the same 失效
标题翻译：用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置及其制造方法
公开(公告)号：US5821765A
公开(公告)日：1998-10-13
申请号：US900013
申请日：1997-07-24
申请人： Zhi-Min Ling , Yung-Tao Lin , Ying Shiau
发明人： Zhi-Min Ling , Yung-Tao Lin , Ying Shiau
IPC分类号： H01L23/544 , G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002
摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively suicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.
摘要翻译：用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。第二实施例选择性地使源极 - 漏极电阻器的暴露部分自动化，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

6. 发明授权

US5761064A Defect management system for productivity and yield improvement 失效
标题翻译：缺陷管理系统提高生产率和产量
公开(公告)号：US5761064A
公开(公告)日：1998-06-02
申请号：US539913
申请日：1995-10-06
申请人： Tho Le La , Ying Shiau
发明人： Tho Le La , Ying Shiau
IPC分类号： G01R31/319 , H01L21/66 , G06F19/00
CPC分类号： H01L22/20 , G01R31/319
摘要： An automated wafer defect management system in which wafer defect data are collected from wafer inspection instruments, converted into a standard data format and made available through a central database system to workstations for review, analysis, and evaluation.
摘要翻译：一种自动晶片缺陷管理系统，其中晶圆缺陷数据从晶圆检测仪器采集，转换为标准数据格式，并通过中央数据库系统提供给工作站进行审查，分析和评估。

7. 发明授权

US5963780A Method for detecting defect sizes in polysilicon and source-drain semiconductor devices 失效
标题翻译：用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的方法
公开(公告)号：US5963780A
公开(公告)日：1999-10-05
申请号：US899739
申请日：1997-07-24
申请人： Zhi-Min Ling , Yung-Tao Lin , Ying Shiau
发明人： Zhi-Min Ling , Yung-Tao Lin , Ying Shiau
IPC分类号： H01L23/544 , H01L21/66 , G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002
摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.
摘要翻译：用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。第二实施例选择性地硅化源极 - 漏极电阻器的暴露部分，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

8. 发明授权

US5896294A Method and apparatus for inspecting manufactured products for defects in response to in-situ monitoring 失效
标题翻译：用于检查制造产品的方法和装置，以响应原位监测的缺陷
公开(公告)号：US5896294A
公开(公告)日：1999-04-20
申请号：US815353
申请日：1997-03-11
申请人： Wanyee Apple Chow , Ming C. Chen , Yung-Tao Lin , Ying Shiau
发明人： Wanyee Apple Chow , Ming C. Chen , Yung-Tao Lin , Ying Shiau
IPC分类号： G05B19/418 , G06F19/00 , G06G7/64 , G06G7/66
CPC分类号： G05B19/41875 , Y02P90/14 , Y02P90/18 , Y02P90/22
摘要： An apparatus and method for selecting products to inspect for defects performs in-situ monitoring of a processing tool during a manufacturing processing step. The data from the in-situ monitoring for a test run of products is correlated by a neural network with data collected during inspection of the test products for defects. During a production run of products, the in-situ monitor data is provided to the neural network which, based on the input data and the correlation, predicts the values of the data that would be collected upon inspection of the products. Specific products from the production run are selected for inspection based upon the predicted values.
摘要翻译：用于选择检查缺陷的产品的装置和方法在制造处理步骤期间执行对处理工具的原位监测。来自产品测试运行的现场监测的数据通过神经网络与在检查产品缺陷检查期间收集的数据相关联。在产品的生产运行期间，将原位监测数据提供给神经网络，神经网络根据输入数据和相关性预测在检查产品时收集的数据的值。根据预测值选择生产运行中的具体产品进行检查。

9. 发明授权

US5716856A Arrangement and method for detecting sequential processing effects in manufacturing using predetermined sequences within runs 失效
公开(公告)号：US5716856A
公开(公告)日：1998-02-10
申请号：US517960
申请日：1995-08-22
申请人： Yung-Tao Lin , Zhi-Min Ling , James Pak , Ying Shiau
发明人： Yung-Tao Lin , Zhi-Min Ling , James Pak , Ying Shiau
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , Y10S148/162
摘要： An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data. These steps are repeated for subsequent sets of the products, so that although the specified processing sequence is different for each of the individual process steps for a set of products, the same processing sequences for the individual processing steps are used for subsequent sets of the products to be manufactured. Since the processing sequences are not randomized from set to set and do not have to be provided to a database, the amounts of interfacing and disk storage needed are greatly reduced.

10. 发明授权

US6001663A Apparatus for detecting defect sizes in polysilicon and source-drain semiconductor devices and method for making the same 失效
标题翻译：用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置及其制造方法
公开(公告)号：US6001663A
公开(公告)日：1999-12-14
申请号：US280997
申请日：1999-03-30
申请人： Zhi-Min Ling , Yung-Tao Lin , Ying Shiau
发明人： Zhi-Min Ling , Yung-Tao Lin , Ying Shiau
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , H01L2924/0002
摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.
摘要翻译：用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。第二实施例选择性地硅化源极 - 漏极电阻器的暴露部分，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

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