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1. 发明授权

US6063531A Focus monitor structure and method for lithography process 失效
标题翻译：光刻工艺的聚焦监视器结构和方法
公开(公告)号：US6063531A
公开(公告)日：2000-05-16
申请号：US167417
申请日：1998-10-06
申请人： Bhanwar Singh , Bharath Rangarajan , Khoi Anh Phan , Carmen L. Morales
发明人： Bhanwar Singh , Bharath Rangarajan , Khoi Anh Phan , Carmen L. Morales
IPC分类号： G03F7/20 , G03F9/02 , G03F9/00
CPC分类号： G03F7/70625 , G03F7/70641
摘要： A focus monitor structure is placed on a reticle or mask near the production device structures, such as integrated circuits, to monitor the focal conditions of the lithography process as well as other parameters, such as the critical dimension, and proximity effects. The focus monitor structure includes a series of densely packed parallel lines and an isolated line along with a line that is positioned orthogonally to the densely packed lines forming an "L" shaped structure. The focus monitor structure also includes a plurality of rectangular islands that create post structures when patterned in the resist layer. The lines of the focus monitor structure are approximately the critical dimension and the rectangular islands vary in width between .+-.10% of the critical dimension. By manually or automatically inspecting the focus monitor structure after it is patterned into a layer of resist, including measuring the width of the resist lines and the resist profile angle of the orthogonal line, information relating to the critical dimension as well as the focal conditions of the lithography process can be determined.
摘要翻译：将聚焦监视器结构放置在生产设备结构（例如集成电路）附近的掩模版或掩模上，以监视光刻工艺的焦点状况以及其他参数，例如临界尺寸和邻近效应。聚焦监视器结构包括一系列密集的平行线和一条隔离的线以及一条线，该线与形成“L”形结构的密集线相正交。聚焦监视器结构还包括当在抗蚀剂层中图案化时产生柱结构的多个矩形岛。聚焦监视器结构的线条大致是临界尺寸，矩形岛的宽度在临界尺寸的+/- 10％之间变化。在聚焦监视器结构被图案化成抗蚀剂层之后，通过手动或自动地检查聚焦监视器结构，包括测量抗蚀剂线的宽度和正交线的抗蚀剂轮廓角，与关键尺寸以及焦点监视结构的焦点条件可以确定光刻工艺。

2. 发明授权

US5886909A Defect diagnosis using simulation for IC yield improvement 失效
标题翻译：缺陷诊断使用模拟IC产量提高
公开(公告)号：US5886909A
公开(公告)日：1999-03-23
申请号：US994960
申请日：1997-12-19
申请人： Linda Milor , Yeng-Kaung Peng , Khoi Anh Phan , David Steele
发明人： Linda Milor , Yeng-Kaung Peng , Khoi Anh Phan , David Steele
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： H01L22/20
摘要： Defects in integrated circuit wafers (10) are often difficult to diagnose, because patterned wafer inspections can only be done after certain wafer processing steps. Defect simulation is used to understand the relation between defects in the wafer (10) and the resulting wafer profiles. Defects such as particles (50) and bubbles (22) in the photoresist (28), for example, translate into a wide variety of defective profiles. Knowledge of the relation between defects and the defect profiles can assist in yield improvement efforts, since defects may be diagnosed by comparing simulated and observed defect profiles. From the simulated defect profiles, methods can be adapted to fix or correct observed defects.
摘要翻译：集成电路晶片（10）中的缺陷通常难以诊断，因为图案化晶片检查只能在某些晶片处理步骤之后进行。使用缺陷模拟来了解晶片（10）中的缺陷与所得晶片轮廓之间的关系。例如，光致抗蚀剂（28）中的诸如颗粒（50）和气泡（22）的缺陷转化成各种缺陷型材。了解缺陷和缺陷轮廓之间的关系可以帮助改善产量，因为可以通过比较模拟和观察到的缺陷轮廓来诊断缺陷。根据模拟的缺陷轮廓，可以调整方法来修正或纠正观察到的缺陷。

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