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1. 发明授权

US06472715B1 Reduced soft error rate (SER) construction for integrated circuit structures 有权
标题翻译：降低集成电路结构的软错误率（SER）结构
公开(公告)号：US06472715B1
公开(公告)日：2002-10-29
申请号：US09675109
申请日：2000-09-28
申请人： Yauh-Ching Liu , Helmut Puchner , Ruggero Castagnetti , Weiran Kong , Lee Phan , Franklin Duan , Steven Michael Peterson
发明人： Yauh-Ching Liu , Helmut Puchner , Ruggero Castagnetti , Weiran Kong , Lee Phan , Franklin Duan , Steven Michael Peterson
IPC分类号： H01L2976
CPC分类号： H01L21/823892 , H01L27/11
摘要： An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 &mgr;m SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 &mgr;m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 &mgr;m. The deep N well of the 0.25 &mgr;m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 &mgr;m, and preferably at least about 2 &mgr;m. In a preferred embodiment, the implantation of the substrate to form the deep N well of the improved SRAM of the invention is carried out in a manner which will cause straggle, i.e., cause the doped volume comprising the deep N well to broaden at its base. Such a broadened base deep N well will have enhanced opportunity to collect electrons generated by the alpha particle collision with the substrate. This deep N well with a broadened base can be formed either by increasing the implant energy or by tilting the substrate with respect to the axis of the implant beam while implanting the substrate to form the deep N well.
摘要翻译：诸如SRAM结构的集成电路结构，其中软错误率被降低包括形成在半导体衬底中的集成电路结构，其中至少一个N沟道晶体管被构建在邻近一个或多个深N阱的P阱中，高压电源和深N阱从衬底的表面向下延伸到衬底中的至少等于α粒子产生的电子 - 空穴对可以有效地引起SRAM单元中的软错误的深度的深度。对于具有一个或多个常规深度不超过约0.5μm的N个阱的0.25μmSRAM设计，α粒子产生的电子 - 空穴对可以有效地引起SRAM单元中的软误差的深度为1至3μm 。因此，0.25μmSRAM设计的深N阱从衬底表面向下延伸至少约1um，优选至少约2μm的距离。在优选实施例中，衬底的注入以形成本发明的改进的SRAM的深N阱以将导致分段的方式进行，即，使得包括深N阱的掺杂体积在其基极处变宽。这样扩大的基底深N阱将增加收集由α粒子与基底碰撞产生的电子的机会。可以通过增加植入能量或通过相对于植入物束的轴线倾斜衬底同时植入衬底以形成深N阱来形成具有加宽基底的该深N阱。

2. 发明授权

US06442061B1 Single channel four transistor SRAM 有权
标题翻译：单通道四晶体管SRAM
公开(公告)号：US06442061B1
公开(公告)日：2002-08-27
申请号：US09783653
申请日：2001-02-14
申请人： Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
发明人： Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
IPC分类号： G11C1100
CPC分类号： G11C11/412 , H01L27/11
摘要： A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type. The first state node transistor has a gate oxide with a second thickness. The source of the first state node transistor is electrically connected to the first state node, and the drain of the first state node transistor is electrically connected to a ground line. The gate of the first state node is electrically connected to the second state node. A second state node transistor is also formed of the first transistor type. The second state node transistor also has a gate oxide with the second thickness. The source of the second state node transistor is electrically connected to the second state node, and the drain of the second state node transistor is electrically connected to the ground line. The gate of the second state node is electrically connected to the first state node.
摘要翻译：根据本发明的形成存储单元的方法。第一栅极晶体管由第一晶体管形成。第一栅极晶体管具有第一厚度的栅极氧化物。第一栅极晶体管的源极电连接到第一位线，并且第一栅极晶体管的漏极电连接到第一状态节点。第一栅极晶体管的栅极电连接到存储器单元使能线。第二栅极晶体管也由第一晶体管形成。第二栅极晶体管还具有第一厚度的栅极氧化物。第二栅极晶体管的源极电连接到第二位线，并且第二栅极晶体管的漏极电连接到第二状态节点。第二通栅晶体管的栅极电连接到存储单元使能线。第一状态节点晶体管也由第一晶体管类型形成。第一状态节点晶体管具有第二厚度的栅极氧化物。第一状态节点晶体管的源极电连接到第一状态节点，并且第一状态节点晶体管的漏极电连接到接地线。第一状态节点的门电连接到第二状态节点。第二状态节点晶体管也由第一晶体管类型形成。第二状态节点晶体管也具有第二厚度的栅极氧化物。第二状态节点晶体管的源极电连接到第二状态节点，并且第二状态节点晶体管的漏极电连接到接地线。第二状态节点的门电连接到第一状态节点。

3. 发明授权

US06566730B1 Laser-breakable fuse link with alignment and break point promotion structures 有权
公开(公告)号：US06566730B1
公开(公告)日：2003-05-20
申请号：US09723476
申请日：2000-11-27
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Shiva Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Shiva Ramesh
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam. The vertically configured structure may be a reduced vertical thickness of the severable portion, an elevated lower surface of the severable portion above adjoining portions of the fuse link, a protrusion which supports the severable portion at a height greater than a height of the adjoining portions of the fuse link, flowing the melted severable portion down sloped surfaces away from a break point, and a propellent material beneath the severable portion which explodes to ablate the severable portion.

4. 发明授权

US06218276B1 Silicide encapsulation of polysilicon gate and interconnect 失效
标题翻译：多晶硅栅极和互连的硅化物封装
公开(公告)号：US06218276B1
公开(公告)日：2001-04-17
申请号：US08995875
申请日：1997-12-22
申请人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
发明人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： H01L213205
CPC分类号： H01L29/4983 , H01L21/28105 , H01L21/28518 , H01L29/66575
摘要： Provided is a method of forming a silicide layer on the top and sidewall surfaces of a polysilicon gate/interconnect in a MOS transistor and on the exposed surfaces of the source and drain regions of the transistor. Devices produced according to the present invention may have different types of silicide formed on their gate and their source/drain electrodes. The invention achieves the advantages of silicide encapsulation of a polysilicon gate in an MOS transistor while also providing silicidation of the source/drain regions of the transistor, thereby reducing electrode resistivity in the transistor and interconnect.
摘要翻译：提供了在MOS晶体管中的多晶硅栅/互连的顶壁和侧壁表面以及晶体管的源极和漏极区域的暴露表面上形成硅化物层的方法。根据本发明生产的器件可以在其栅极及其源极/漏极上形成不同类型的硅化物。本发明实现了MOS晶体管中多晶硅栅极的硅化物封装的优点，同时还提供了晶体管的源极/漏极区域的硅化，从而降低了晶体管和互连中的电极电阻率。

5. 发明授权

US6061264A Self-aligned fuse structure and method with anti-reflective coating 失效
标题翻译：自对准保险丝结构和防反射涂层方法
公开(公告)号：US6061264A
公开(公告)日：2000-05-09
申请号：US118602
申请日：1998-07-17
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
IPC分类号： G11C17/14 , G11C11/42 , G11C13/04
CPC分类号： G11C17/14
摘要： Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithography and an anti-reflective coating. The self-alignment allows the size and location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages, including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less time-consuming, which increases throughput in fabrication.
摘要翻译：提供了自对准的半导体熔丝结构，制造这种熔丝结构的方法，以及结合这样的熔丝结构的装置。保险丝断点，熔断器的电气连接部分被激光束切断的点，通过使用光刻和抗反射涂层进行自对准。自对准允许断点的尺寸和位置对激光束的尺寸和对准不太敏感。这具有几个优点，包括允许光刻控制和激光光斑照射熔丝材料和周围结构的有效尺寸减小。这允许减小熔丝间距，增加密度和使用芯片面积的效率，并且导致减少的热暴露，这对芯片造成较小的损坏。此外，激光对准不太关键，因此耗时更少，这增加了制造中的吞吐量。

6. 发明授权

US6037233A Metal-encapsulated polysilicon gate and interconnect 失效
标题翻译：金属封装的多晶硅栅极和互连
公开(公告)号：US6037233A
公开(公告)日：2000-03-14
申请号：US69027
申请日：1998-04-27
申请人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
发明人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49
CPC分类号： H01L29/66515 , H01L21/28105 , H01L29/4983 , H01L29/66575
摘要： Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.
摘要翻译：提供了在MOS晶体管中的多晶硅栅电极/互连的水平和垂直表面上形成金属层的方法，以及具有金属封装的栅极和互连的器件。本发明的金属封装方法还可以在晶体管的源极和漏极区域的暴露表面上提供金属层。本发明的方法和装置允许减少器件电阻和信号传播延迟。

7. 发明授权

US06806551B2 Fuse construction for integrated circuit structure having low dielectric constant dielectric material 有权
标题翻译：具有低介电常数介电材料的集成电路结构的保险丝结构
公开(公告)号：US06806551B2
公开(公告)日：2004-10-19
申请号：US10376401
申请日：2003-02-28
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L23/5329 , H01L2224/05022 , H01L2924/01019
摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
摘要翻译：保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

8. 发明授权

US06566171B1 Fuse construction for integrated circuit structure having low dielectric constant dielectric material 有权
标题翻译：具有低介电常数介电材料的集成电路结构的保险丝结构
公开(公告)号：US06566171B1
公开(公告)日：2003-05-20
申请号：US09882404
申请日：2001-06-12
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L23/5329 , H01L2224/05022 , H01L2924/01019
摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
摘要翻译：保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

9. 发明授权

US6066525A Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process 有权
标题翻译：通过在CMOS工艺中形成单独的电介质层来形成DRAM电容器的方法
公开(公告)号：US6066525A
公开(公告)日：2000-05-23
申请号：US365455
申请日：1999-08-02
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Subramanian Ramesh
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1085 , H01L27/10805
摘要： Disclosed are planar DRAM cells including a storage capacitor having a high dielectric constant capacitor dielectric. The DRAM cell also includes an access transistor having a gate dielectric which does not include the high dielectric constant material. A single polysilicon layer is employed to form the gate electrode of the access transistor and a reference plate of the storage capacitor. A disclosed fabrication process forms the high dielectric constant material that is limited to a capacitor region of the DRAM cell and then forms the gate dielectric over an entire active region including both the high dielectric constant material layer at the capacitor region and the semiconductor substrate at the access transistor region. In this manner, a high quality gate dielectric (e.g., silicon oxide) is formed at the access transistor region and a high dielectric constant dielectric layer (e.g., silicon nitride) is formed at the capacitor region. A capacitor plate and a gate electrode are formed by patterning the same conductive layer (e.g., doped polysilicon) formed over top of the gate dielectric.
摘要翻译：公开了包括具有高介电常数电容器电介质的存储电容器的平面DRAM单元。 DRAM单元还包括具有不包括高介电常数材料的栅极电介质的存取晶体管。采用单个多晶硅层形成存取晶体管的栅极电极和存储电容器的参考板。所公开的制造工艺形成了限于DRAM单元的电容器区域的高介电常数材料，然后在包括电容器区域的高介电常数材料层和在半导体衬底的整个有源区域上形成栅极电介质存取晶体管区。以这种方式，在存取晶体管区域形成高质量的栅极电介质（例如氧化硅），并且在电容器区域形成高介电常数介电层（例如氮化硅）。通过对在栅极电介质的顶部上形成的相同导电层（例如，掺杂多晶硅）进行构图来形成电容器板和栅电极。

10. 发明授权

US5953614A Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step 失效
标题翻译：使用单一硅化物形成步骤形成用于MOS结构的自对准金属硅化物接触的工艺
公开(公告)号：US5953614A
公开(公告)日：1999-09-14
申请号：US947742
申请日：1997-10-09
申请人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
发明人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/60 , H01L23/485
CPC分类号： H01L21/76897 , H01L23/485 , H01L29/665 , H01L29/6656 , H01L29/66575 , H01L21/2652 , H01L21/28052 , H01L29/66545 , H01L29/6659 , H01L2924/0002
摘要： A process is described for forming self-aligned contacts to an MOS device on an integrated circuit structure characterized by the simultaneous formation of the metal silicide gate portion and the metal silicide source/drain portions. The process comprises forming a gate oxide layer on a silicon substrate, forming a polysilicon gate electrode layer over the gate oxide layer, and forming a layer of a first insulation material over the polysilicon gate electrode layer. Metal silicide is simultaneously formed on the exposed surface of the polysilicon gate electrode and over the exposed portions of the silicon substrate. Source/drain regions are formed in the silicon substrate, either before or after formation of the metal silicide over the exposed portions of the silicon substrate, whereby the metal silicide portions on the substrate above the source/drain regions are in electrical communication with the source/drain regions.
摘要翻译：描述了用于在集成电路结构上形成与MOS器件的自对准接触的过程，其特征在于同时形成金属硅化物栅极部分和金属硅化物源极/漏极部分。该工艺包括在硅衬底上形成栅极氧化层，在栅氧化层上形成多晶硅栅电极层，并在多晶硅栅电极层上形成第一绝缘材料层。金属硅化物同时形成在多晶硅栅电极的暴露表面上以及硅衬底的暴露部分上。在硅衬底的暴露部分上形成金属硅化物之前或之后，在硅衬底中形成源极/漏极区，由此源极/漏极区上方的衬底上的金属硅化物部分与源极电连通 /漏区。

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