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1. 发明授权

US06218276B1 Silicide encapsulation of polysilicon gate and interconnect 失效
标题翻译：多晶硅栅极和互连的硅化物封装
公开(公告)号：US06218276B1
公开(公告)日：2001-04-17
申请号：US08995875
申请日：1997-12-22
申请人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
发明人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： H01L213205
CPC分类号： H01L29/4983 , H01L21/28105 , H01L21/28518 , H01L29/66575
摘要： Provided is a method of forming a silicide layer on the top and sidewall surfaces of a polysilicon gate/interconnect in a MOS transistor and on the exposed surfaces of the source and drain regions of the transistor. Devices produced according to the present invention may have different types of silicide formed on their gate and their source/drain electrodes. The invention achieves the advantages of silicide encapsulation of a polysilicon gate in an MOS transistor while also providing silicidation of the source/drain regions of the transistor, thereby reducing electrode resistivity in the transistor and interconnect.
摘要翻译：提供了在MOS晶体管中的多晶硅栅/互连的顶壁和侧壁表面以及晶体管的源极和漏极区域的暴露表面上形成硅化物层的方法。根据本发明生产的器件可以在其栅极及其源极/漏极上形成不同类型的硅化物。本发明实现了MOS晶体管中多晶硅栅极的硅化物封装的优点，同时还提供了晶体管的源极/漏极区域的硅化，从而降低了晶体管和互连中的电极电阻率。

2. 发明授权

US6061264A Self-aligned fuse structure and method with anti-reflective coating 失效
标题翻译：自对准保险丝结构和防反射涂层方法
公开(公告)号：US6061264A
公开(公告)日：2000-05-09
申请号：US118602
申请日：1998-07-17
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
IPC分类号： G11C17/14 , G11C11/42 , G11C13/04
CPC分类号： G11C17/14
摘要： Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithography and an anti-reflective coating. The self-alignment allows the size and location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages, including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less time-consuming, which increases throughput in fabrication.
摘要翻译：提供了自对准的半导体熔丝结构，制造这种熔丝结构的方法，以及结合这样的熔丝结构的装置。保险丝断点，熔断器的电气连接部分被激光束切断的点，通过使用光刻和抗反射涂层进行自对准。自对准允许断点的尺寸和位置对激光束的尺寸和对准不太敏感。这具有几个优点，包括允许光刻控制和激光光斑照射熔丝材料和周围结构的有效尺寸减小。这允许减小熔丝间距，增加密度和使用芯片面积的效率，并且导致减少的热暴露，这对芯片造成较小的损坏。此外，激光对准不太关键，因此耗时更少，这增加了制造中的吞吐量。

3. 发明授权

US6037233A Metal-encapsulated polysilicon gate and interconnect 失效
标题翻译：金属封装的多晶硅栅极和互连
公开(公告)号：US6037233A
公开(公告)日：2000-03-14
申请号：US69027
申请日：1998-04-27
申请人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
发明人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49
CPC分类号： H01L29/66515 , H01L21/28105 , H01L29/4983 , H01L29/66575
摘要： Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.
摘要翻译：提供了在MOS晶体管中的多晶硅栅电极/互连的水平和垂直表面上形成金属层的方法，以及具有金属封装的栅极和互连的器件。本发明的金属封装方法还可以在晶体管的源极和漏极区域的暴露表面上提供金属层。本发明的方法和装置允许减少器件电阻和信号传播延迟。

4. 发明授权

US6066525A Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process 有权
标题翻译：通过在CMOS工艺中形成单独的电介质层来形成DRAM电容器的方法
公开(公告)号：US6066525A
公开(公告)日：2000-05-23
申请号：US365455
申请日：1999-08-02
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Subramanian Ramesh
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1085 , H01L27/10805
摘要： Disclosed are planar DRAM cells including a storage capacitor having a high dielectric constant capacitor dielectric. The DRAM cell also includes an access transistor having a gate dielectric which does not include the high dielectric constant material. A single polysilicon layer is employed to form the gate electrode of the access transistor and a reference plate of the storage capacitor. A disclosed fabrication process forms the high dielectric constant material that is limited to a capacitor region of the DRAM cell and then forms the gate dielectric over an entire active region including both the high dielectric constant material layer at the capacitor region and the semiconductor substrate at the access transistor region. In this manner, a high quality gate dielectric (e.g., silicon oxide) is formed at the access transistor region and a high dielectric constant dielectric layer (e.g., silicon nitride) is formed at the capacitor region. A capacitor plate and a gate electrode are formed by patterning the same conductive layer (e.g., doped polysilicon) formed over top of the gate dielectric.
摘要翻译：公开了包括具有高介电常数电容器电介质的存储电容器的平面DRAM单元。 DRAM单元还包括具有不包括高介电常数材料的栅极电介质的存取晶体管。采用单个多晶硅层形成存取晶体管的栅极电极和存储电容器的参考板。所公开的制造工艺形成了限于DRAM单元的电容器区域的高介电常数材料，然后在包括电容器区域的高介电常数材料层和在半导体衬底的整个有源区域上形成栅极电介质存取晶体管区。以这种方式，在存取晶体管区域形成高质量的栅极电介质（例如氧化硅），并且在电容器区域形成高介电常数介电层（例如氮化硅）。通过对在栅极电介质的顶部上形成的相同导电层（例如，掺杂多晶硅）进行构图来形成电容器板和栅电极。

5. 发明授权

US5953614A Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step 失效
标题翻译：使用单一硅化物形成步骤形成用于MOS结构的自对准金属硅化物接触的工艺
公开(公告)号：US5953614A
公开(公告)日：1999-09-14
申请号：US947742
申请日：1997-10-09
申请人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
发明人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/60 , H01L23/485
CPC分类号： H01L21/76897 , H01L23/485 , H01L29/665 , H01L29/6656 , H01L29/66575 , H01L21/2652 , H01L21/28052 , H01L29/66545 , H01L29/6659 , H01L2924/0002
摘要： A process is described for forming self-aligned contacts to an MOS device on an integrated circuit structure characterized by the simultaneous formation of the metal silicide gate portion and the metal silicide source/drain portions. The process comprises forming a gate oxide layer on a silicon substrate, forming a polysilicon gate electrode layer over the gate oxide layer, and forming a layer of a first insulation material over the polysilicon gate electrode layer. Metal silicide is simultaneously formed on the exposed surface of the polysilicon gate electrode and over the exposed portions of the silicon substrate. Source/drain regions are formed in the silicon substrate, either before or after formation of the metal silicide over the exposed portions of the silicon substrate, whereby the metal silicide portions on the substrate above the source/drain regions are in electrical communication with the source/drain regions.
摘要翻译：描述了用于在集成电路结构上形成与MOS器件的自对准接触的过程，其特征在于同时形成金属硅化物栅极部分和金属硅化物源极/漏极部分。该工艺包括在硅衬底上形成栅极氧化层，在栅氧化层上形成多晶硅栅电极层，并在多晶硅栅电极层上形成第一绝缘材料层。金属硅化物同时形成在多晶硅栅电极的暴露表面上以及硅衬底的暴露部分上。在硅衬底的暴露部分上形成金属硅化物之前或之后，在硅衬底中形成源极/漏极区，由此源极/漏极区上方的衬底上的金属硅化物部分与源极电连通 /漏区。

6. 发明授权

US06413848B1 Self-aligned fuse structure and method with dual-thickness dielectric 有权
标题翻译：自对准保险丝结构和双层电介质的方法
公开(公告)号：US06413848B1
公开(公告)日：2002-07-02
申请号：US09534907
申请日：2000-03-23
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
IPC分类号： H01L2144
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned anti-reflective dielectric coatings. The self-alignment allows the size location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less timely, which increases throughput in fabrication.
摘要翻译：提供了自对准的半导体熔丝结构，制造这种熔丝结构的方法，以及结合这样的熔丝结构的装置。保险丝断点，其中熔断器的电连接部分被激光束切断的点通过使用光刻图案的抗反射电介质涂层自对准。自对准允许断点的尺寸位置对激光束尺寸和对准不那么敏感。这具有几个优点，包括允许光刻控制和激光点照射熔丝材料和周围结构的有效尺寸减小。这允许减小熔丝间距，增加密度和使用芯片面积的效率，并且导致减少的热暴露，这对芯片造成较小的损坏。此外，激光对准不太关键，因此不及时，这增加了制造的吞吐量。

7. 发明授权

US06259146B1 Self-aligned fuse structure and method with heat sink 失效
标题翻译：自对准保险丝结构及散热方式
公开(公告)号：US06259146B1
公开(公告)日：2001-07-10
申请号：US09118232
申请日：1998-07-17
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned dielectric and a heat sink material. The self-alignment allows the size and location of the break point to be more forgiving of the laser beam size and alignment. This has several advantages, including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less time-consuming, which increases throughput in fabrication. The present invention exploits the characteristic of most dielectric materials that they are poor conductors of thermal energy. Thermal resistance increases with the thickness of the dielectric. Thus that heat is conducted more easily and thus quickly through a relatively thin portion of dielectric than it is through a relatively thick portion of dielectric. In alternative embodiments, the present invention also exploits the characteristic of a dielectric material that its reflectance changes with its thickness due to optical interference effects. In such embodiments, the self-alignment of the fuse break point is further facilitated by the use of photolithography and anti-reflective coatings.
摘要翻译：提供了自对准的半导体熔丝结构，制造这种熔丝结构的方法，以及结合这样的熔丝结构的装置。保险丝断点，熔丝部分的电连接部分被激光束切断的点，通过使用光刻图案化电介质和散热材料自对准。自对准允许断点的尺寸和位置更宽容激光束尺寸和对准。这具有几个优点，包括允许光刻控制和激光光斑照射熔丝材料和周围结构的有效尺寸减小。这允许减小熔丝间距，增加密度和使用芯片面积的效率，并且导致减少的热暴露，这对芯片造成较小的损坏。此外，激光对准不太关键，因此耗时更少，这增加了制造中的生产量。本发明利用大多数介电材料的特性，它们是不良的热能导体。热阻随电介质的厚度而增加。因此，通过电介质的相对较薄的部分比通过电介质的相对较厚的部分，热更容易地传导并且因此被快速地传导。在替代实施例中，本发明还利用介电材料的特性，其反射率由于光学干涉效应而随其厚度而变化。在这样的实施例中，通过使用光刻和抗反射涂层进一步促进了熔断器断点的自对准。

8. 发明授权

US6166403A Integrated circuit having embedded memory with electromagnetic shield 失效
标题翻译：具有电磁屏蔽的嵌入式存储器的集成电路
公开(公告)号：US6166403A
公开(公告)日：2000-12-26
申请号：US967545
申请日：1997-11-12
申请人： Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
发明人： Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/552 , H01L23/60 , H01L27/10 , H01L27/105 , H01L23/48 , H01L29/00
CPC分类号： H01L23/552 , H01L23/60 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a substrate having a memory area and a non-memory area. An embedded memory is fabricated on the substrate within the memory area. First and second semiconductor cells are fabricated on the substrate within the non-memory area. An electromagnetic shield covers substantially memory area. A routing layer is fabricated over the memory and non-memory areas and over the electromagnetic shield. A signal wire is electrically coupled between the first and second semiconductor cells and has a conductive segment which is routed within the routing layer and extends over the memory area.
摘要翻译：一种集成电路，包括具有存储区和非存储区的衬底。在存储区内的衬底上制造嵌入式存储器。在非存储区域内的衬底上制造第一和第二半导体单元。电磁屏蔽基本上覆盖存储区域。在存储器和非存储器区域以及电磁屏蔽上制造布线层。信号线电耦合在第一和第二半导体单元之间，并且具有在路由层内布线并在存储区域上延伸的导电段。

9. 发明授权

US6162714A Method of forming thin polygates for sub quarter micron CMOS process 失效
标题翻译：形成亚微米CMOS工艺的薄多孔栅的方法
公开(公告)号：US6162714A
公开(公告)日：2000-12-19
申请号：US991397
申请日：1997-12-16
申请人： Ruggero Castagnetti , Yauh-Ching Liu , Gary Giust , Subramanian Ramesh
发明人： Ruggero Castagnetti , Yauh-Ching Liu , Gary Giust , Subramanian Ramesh
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method is provided for forming thin polysilicon transistor gates using dual doped polysilicon without reducing the ion implant energy. The method comprises depositing polysilicon over a region of a substrate, masking and implanting the polysilicon with dopant impurities to form the channel regions of one conductivity type, and removing the photo resist mask. The polysilicon layer is then masked to define the channel regions of the opposite conductivity type and is implanted with dopant impurities of the opposite conductivity type. Following the dual ion implantation, the photo resist mask is removed and the substrate may be annealed to activate the dopants in the polysilicon. The dual doped polysilicon layer is then polished using a chemical-mechanical polish to achieve a desired thickness for the polysilicon transistor gates. The polysilicon is subsequently masked and etched to define the polysilicon transistor gates.
摘要翻译：提供了一种使用双掺杂多晶硅形成薄多晶硅晶体管栅极而不减少离子注入能量的方法。该方法包括在衬底的区域上沉积多晶硅，用掺杂杂质掩蔽和注入多晶硅以形成一种导电类型的沟道区，以及去除光刻胶掩模。然后掩模多晶硅层以限定相反导电类型的沟道区，并注入相反导电类型的掺杂杂质。在双离子注入之后，除去光致抗蚀剂掩模，并且可以将衬底退火以激活多晶硅中的掺杂剂。然后使用化学机械抛光对双掺杂多晶硅层进行抛光，以达到多晶硅晶体管栅极所需的厚度。随后掩模和蚀刻多晶硅以限定多晶硅晶体管栅极。

10. 发明授权

US06566730B1 Laser-breakable fuse link with alignment and break point promotion structures 有权
公开(公告)号：US06566730B1
公开(公告)日：2003-05-20
申请号：US09723476
申请日：2000-11-27
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Shiva Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Shiva Ramesh
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam. The vertically configured structure may be a reduced vertical thickness of the severable portion, an elevated lower surface of the severable portion above adjoining portions of the fuse link, a protrusion which supports the severable portion at a height greater than a height of the adjoining portions of the fuse link, flowing the melted severable portion down sloped surfaces away from a break point, and a propellent material beneath the severable portion which explodes to ablate the severable portion.

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