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1. 发明授权

US06442061B1 Single channel four transistor SRAM 有权
标题翻译：单通道四晶体管SRAM
公开(公告)号：US06442061B1
公开(公告)日：2002-08-27
申请号：US09783653
申请日：2001-02-14
申请人： Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
发明人： Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
IPC分类号： G11C1100
CPC分类号： G11C11/412 , H01L27/11
摘要： A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type. The first state node transistor has a gate oxide with a second thickness. The source of the first state node transistor is electrically connected to the first state node, and the drain of the first state node transistor is electrically connected to a ground line. The gate of the first state node is electrically connected to the second state node. A second state node transistor is also formed of the first transistor type. The second state node transistor also has a gate oxide with the second thickness. The source of the second state node transistor is electrically connected to the second state node, and the drain of the second state node transistor is electrically connected to the ground line. The gate of the second state node is electrically connected to the first state node.
摘要翻译：根据本发明的形成存储单元的方法。第一栅极晶体管由第一晶体管形成。第一栅极晶体管具有第一厚度的栅极氧化物。第一栅极晶体管的源极电连接到第一位线，并且第一栅极晶体管的漏极电连接到第一状态节点。第一栅极晶体管的栅极电连接到存储器单元使能线。第二栅极晶体管也由第一晶体管形成。第二栅极晶体管还具有第一厚度的栅极氧化物。第二栅极晶体管的源极电连接到第二位线，并且第二栅极晶体管的漏极电连接到第二状态节点。第二通栅晶体管的栅极电连接到存储单元使能线。第一状态节点晶体管也由第一晶体管类型形成。第一状态节点晶体管具有第二厚度的栅极氧化物。第一状态节点晶体管的源极电连接到第一状态节点，并且第一状态节点晶体管的漏极电连接到接地线。第一状态节点的门电连接到第二状态节点。第二状态节点晶体管也由第一晶体管类型形成。第二状态节点晶体管也具有第二厚度的栅极氧化物。第二状态节点晶体管的源极电连接到第二状态节点，并且第二状态节点晶体管的漏极电连接到接地线。第二状态节点的门电连接到第一状态节点。

2. 发明授权

US06472715B1 Reduced soft error rate (SER) construction for integrated circuit structures 有权
标题翻译：降低集成电路结构的软错误率（SER）结构
公开(公告)号：US06472715B1
公开(公告)日：2002-10-29
申请号：US09675109
申请日：2000-09-28
申请人： Yauh-Ching Liu , Helmut Puchner , Ruggero Castagnetti , Weiran Kong , Lee Phan , Franklin Duan , Steven Michael Peterson
发明人： Yauh-Ching Liu , Helmut Puchner , Ruggero Castagnetti , Weiran Kong , Lee Phan , Franklin Duan , Steven Michael Peterson
IPC分类号： H01L2976
CPC分类号： H01L21/823892 , H01L27/11
摘要： An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 &mgr;m SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 &mgr;m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 &mgr;m. The deep N well of the 0.25 &mgr;m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 &mgr;m, and preferably at least about 2 &mgr;m. In a preferred embodiment, the implantation of the substrate to form the deep N well of the improved SRAM of the invention is carried out in a manner which will cause straggle, i.e., cause the doped volume comprising the deep N well to broaden at its base. Such a broadened base deep N well will have enhanced opportunity to collect electrons generated by the alpha particle collision with the substrate. This deep N well with a broadened base can be formed either by increasing the implant energy or by tilting the substrate with respect to the axis of the implant beam while implanting the substrate to form the deep N well.
摘要翻译：诸如SRAM结构的集成电路结构，其中软错误率被降低包括形成在半导体衬底中的集成电路结构，其中至少一个N沟道晶体管被构建在邻近一个或多个深N阱的P阱中，高压电源和深N阱从衬底的表面向下延伸到衬底中的至少等于α粒子产生的电子 - 空穴对可以有效地引起SRAM单元中的软错误的深度的深度。对于具有一个或多个常规深度不超过约0.5μm的N个阱的0.25μmSRAM设计，α粒子产生的电子 - 空穴对可以有效地引起SRAM单元中的软误差的深度为1至3μm 。因此，0.25μmSRAM设计的深N阱从衬底表面向下延伸至少约1um，优选至少约2μm的距离。在优选实施例中，衬底的注入以形成本发明的改进的SRAM的深N阱以将导致分段的方式进行，即，使得包括深N阱的掺杂体积在其基极处变宽。这样扩大的基底深N阱将增加收集由α粒子与基底碰撞产生的电子的机会。可以通过增加植入能量或通过相对于植入物束的轴线倾斜衬底同时植入衬底以形成深N阱来形成具有加宽基底的该深N阱。

3. 发明授权

US06455363B1 System to improve ser immunity and punchthrough 有权
标题翻译：提高免疫力和突破的系统
公开(公告)号：US06455363B1
公开(公告)日：2002-09-24
申请号：US09609527
申请日：2000-07-03
申请人： Helmut Puchner , Gary K. Giust , Weiran Kong
发明人： Helmut Puchner , Gary K. Giust , Weiran Kong
IPC分类号： H01L218238
CPC分类号： H01L21/76237 , H01L21/823878 , H01L21/823892 , H01L27/0921
摘要： A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device. The additional well tub is deposited to a depth that is shallower than the standard well tub. The additional well tub is deposited using an ion implantation process using the same mask set as that used for the threshold voltage adjustment deposition. Thus, no additional mask layer is required to deposit the additional well tub, and the all of the expenses normally associated with an additional mask layer are avoided.
摘要翻译：一种用于制造具有标准井筒的SRAM装置的方法，其中在标准井筒内沉积附加的井筒。以这种方式，SRAM器件的阱区域中的掺杂剂浓度增加，这增加了器件的隔离穿透容限和SER抗扰性。另外的浴缸被沉积到比标准的井筒浅的深度。使用与用于阈值电压调整沉积的掩模组相同的掩模组，使用离子注入工艺沉积附加的井筒。因此，不需要额外的掩模层来沉积附加的井筒，并且避免了与附加掩模层通常相关联的所有费用。

4. 发明授权

US07098501B2 Thin capacitive structure 有权
标题翻译：薄电容结构
公开(公告)号：US07098501B2
公开(公告)日：2006-08-29
申请号：US10360267
申请日：2003-02-05
申请人： Weiran Kong , Bernard Ho , David Greenhill , Sudhakar Bobba
发明人： Weiran Kong , Bernard Ho , David Greenhill , Sudhakar Bobba
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L28/40 , H01L21/76838 , H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure in a semiconductor device is provided. The capacitor structure includes a first power rail on a topmost level of the semiconductor device, and a second power rail on the topmost level of the semiconductor device. The capacitor structure also includes a dielectric layer disposed over at least a portion of one of the first power rail and the second power rail. The capacitor structure further includes a conductive layer disposed over and between the first power rail and the second power rail where the conductive layer is in electrical contact with the power rail not having the dielectric layer, and the conductive layer is disposed over the dielectric layer.
摘要翻译：提供半导体器件中的电容器结构。电容器结构包括在半导体器件的最上层的第一电源轨和半导体器件的最上层的第二电源轨。电容器结构还包括设置在第一电力轨道和第二电力轨道之一的至少一部分上的电介质层。电容器结构还包括设置在第一电力轨道和第二电力轨道之上和之间的导电层，其中导电层与不具有电介质层的电力轨道电接触，并且导电层设置在介电层上。

5. 发明申请

US20110037119A1 MEMORY 审中-公开
标题翻译：记忆
公开(公告)号：US20110037119A1
公开(公告)日：2011-02-17
申请号：US12988125
申请日：2009-05-13
申请人： Weiran Kong
发明人： Weiran Kong
IPC分类号： H01L29/792
CPC分类号： H01L27/11521 , H01L29/40114
摘要： A memory includes: a semiconductor substrate (1), a doped source area (2) and a doped drain area (3) set in the semiconductor substrate (1), and a channel area (4) set between said doped source area (2) and said doped drain area (3); a first insulating layer (5) located on the semiconductor substrate (1), a charge memory layer (6) composed of polysilicon located on said first insulating layer (5); an SiGe conducting layer (7) set in said charge memory layer (6).
摘要翻译：存储器包括：设置在半导体衬底（1）中的半导体衬底（1），掺杂源区（2）和掺杂漏极区（3），以及设置在所述掺杂源区（2）之间的沟道区）和所述掺杂漏极区（3）; 位于所述半导体衬底（1）上的第一绝缘层（5），由位于所述第一绝缘层（5）上的多晶硅构成的电荷存储层（6）; 设置在所述电荷存储层（6）中的SiGe导电层（7）。

6. 发明授权

US5602445A Blue-violet phosphor for use in electroluminescent flat panel displays 失效
标题翻译：用于电致发光平板显示器的蓝紫色荧光粉
公开(公告)号：US5602445A
公开(公告)日：1997-02-11
申请号：US440203
申请日：1995-05-12
申请人： Rajendra Solanki , Weiran Kong , Shafqat Ahmed
发明人： Rajendra Solanki , Weiran Kong , Shafqat Ahmed
IPC分类号： C09K11/77 , H05B33/14 , H01J1/62
CPC分类号： H05B33/14 , C09K11/7719 , C09K11/772 , C09K11/7732 , C09K11/7733
摘要： A bright, short wavelength blue-violet phosphor for electroluminescent displays comprises an alkaline-based halide as a host material and a rare earth as a dopant. The host alkaline chloride can be chosen from the group II alkaline elements, particularly strontium chloride (SrCl.sub.2) or calcium chloride (CaCl.sub.2), which, with a europium (Eu) or cerium (Ce) rare earth dopant, electroluminesces at a peak wavelength of 404 and 367 nanometers (nm) respectively. The resulting emissions have CIE chromaticity coordinates which lie at the boundary of the visible range for the human eye thereby allowing a greater range of colors for full color flat panel electroluminescent (FPEL) displays.
摘要翻译：用于电致发光显示器的明亮的短波长蓝紫色磷光体包括作为主体材料的碱性卤化物和作为掺杂剂的稀土。主体碱性氯化物可以选自II族碱性元素，特别是氯化锶（SrCl 2）或氯化钙（CaCl 2），其与铕（Eu）或铈（Ce）稀土掺杂剂，以峰值波长 404和367纳米（nm）。所产生的发射具有位于人眼可见光范围边界处的CIE色度坐标，从而允许全色平板电致发光（FPEL）显示器的更大范围的颜色。

7. 发明授权

US08693243B2 Memory array 有权
标题翻译：内存阵列
公开(公告)号：US08693243B2
公开(公告)日：2014-04-08
申请号：US13253855
申请日：2011-10-05
申请人： Jing Gu , Bo Zhang , Weiran Kong , Jian Hu
发明人： Jing Gu , Bo Zhang , Weiran Kong , Jian Hu
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/0458 , G11C16/10 , H01L21/28273 , H01L29/42332 , H01L29/7887
摘要： A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.
摘要翻译：在半导体技术领域中使用的存储器阵列包括多个存储单元，位线，垂直于位线的字线和第一/第二控制线。存储器阵列使用分裂门存储器单元，其中存储器单元的两个存储器位单元共享一个字线，从而可以通过向字线施加不同的电压来实现存储器单元的读取，编程和擦除，两个控制栅极和源极/漏极区域; 字线共享结构使得分闸器闪存能够有效地减小芯片面积并避免过度擦除问题，同时保持芯片的电隔离性能不变，而不会增加工艺的复杂性。

8. 发明申请

US20120206969A1 Memory Array 有权
标题翻译：内存阵列
公开(公告)号：US20120206969A1
公开(公告)日：2012-08-16
申请号：US13253855
申请日：2011-10-05
申请人： Jing Gu , Bo Zhang , Weiran Kong , Jian Hu
发明人： Jing Gu , Bo Zhang , Weiran Kong , Jian Hu
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： G11C16/26 , G11C16/0458 , G11C16/10 , H01L21/28273 , H01L29/42332 , H01L29/7887
摘要： A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.
摘要翻译：在半导体技术领域中使用的存储器阵列包括多个存储单元，位线，垂直于位线的字线和第一/第二控制线。存储器阵列使用分裂门存储器单元，其中存储器单元的两个存储器位单元共享一个字线，从而可以通过向字线施加不同的电压来实现存储器单元的读取，编程和擦除，两个控制栅极和源极/漏极区域; 字线共享结构使得分闸器闪存能够有效地减小芯片面积并避免过度擦除问题，同时保持芯片的电隔离性能不变，而不会增加工艺的复杂性。

9. 发明授权

US5888894A Method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes 失效
标题翻译：在半导体制造工艺中减少垂直表面附近杂散导电材料的方法
公开(公告)号：US5888894A
公开(公告)日：1999-03-30
申请号：US965912
申请日：1997-11-07
申请人： Weiran Kong , Kai-Ning Chang
发明人： Weiran Kong , Kai-Ning Chang
IPC分类号： H01L21/768 , H01L21/28 , H01L21/302
CPC分类号： H01L21/76895
摘要： A method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes comprising the following steps. Deposit the gate oxide, polysilicon and cap oxide layers. Apply a Poly1A mask. The Poly1A mask pattern comprises the Poly1 areas that are part of the final circuit layout as well as additional Poly1 areas that are included to provide planar surfaces to prevent stringer formation. Etch the cap, polysilicon and gate oxide layers to partially form the transistor gate structures. Form oxide spacers on the sides of the transistor gate structures. Apply a source/drain mask. Deposit source/drain dopants to form diffusions. Deposit an interlayer dielectric. Mask and pattern contacts to the diffusions and the Poly1 layer. Deposit blanket TiN/Ti layer(s). Pattern the TiN/Ti layer(s) using a TiN/Ti mask and a dry anisotropic etch. Patterning the TiN/Ti layer(s) may create TiN/Ti stringers along vertical surfaces of the interconnect layer. However, by defining the Poly1A mask pattern to leave Poly1 in pre-defined potential stringer problem areas, these surfaces remain planar and thus free of stringers. Next, apply a Poly1B mask. The Polyl1B mask is defined such that the final Poly1 pattern is the logical AND of the Poly1A mask pattern and the inverse of the Poly1B mask. Then etch the cap, polysilicon and gate oxide layers to complete formation of the transistor gate structures.
摘要翻译：一种用于在半导体制造工艺中减少垂直表面附近的杂散导电材料的方法，包括以下步骤。沉积栅极氧化物，多晶硅和氧化铟层。应用Poly1A面膜。 Poly1A掩模图案包括作为最终电路布局的一部分的Poly1区域以及额外的Poly1区域，其被包括以提供平面表面以防止纵梁形成。蚀刻帽，多晶硅和栅极氧化物层以部分地形成晶体管栅极结构。在晶体管栅极结构的侧面上形成氧化物间隔物。应用源/漏屏蔽。沉积源/漏掺杂物形成扩散。沉积层间电介质掩模和图案与扩散和Poly1层接触。沉积层TiN / Ti层。使用TiN / Ti掩模和干法各向异性蚀刻对TiN / Ti层进行成型。对TiN / Ti层进行图案化可以在互连层的垂直表面上产生TiN / Ti桁条。然而，通过定义Poly1A掩模图案使Poly1保留在预定义的潜在纵向问题区域中，这些表面保持平面，因此没有桁条。接下来，应用Poly1B掩模。定义Polyl1B掩模，使得最终的Poly1图案是Poly1A掩模图案与Poly1B掩模的倒数的逻辑AND。然后蚀刻帽，多晶硅和栅极氧化物层以完成晶体管栅极结构的形成。

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