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    • 2. 发明申请
    • POWER CONTROLLER FOR SOC POWER GATING APPLICATIONS
    • 电源控制器用于SOC功率增益应用
    • US20130057338A1
    • 2013-03-07
    • US13226038
    • 2011-09-06
    • Ramnath VenkatramanShashidhara S. BapatRuggero Castagnetti
    • Ramnath VenkatramanShashidhara S. BapatRuggero Castagnetti
    • H01L25/065
    • H03K19/0016
    • A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.
    • 冲击电流控制器包括连接的时钟模块,以基于对与输入的睡眠控制信号相对应的预设数量的时钟周期计数来提供延迟的睡眠控制信号。 此外,引入电流控制器包括环形振荡器模块,其连接以基于对应于虚拟电源线电压的预设数量的环形振荡器周期来计数延迟的睡眠控制信号。 一种控制加速电流的方法包括:基于对与输入的睡眠控制信号相对应的预设数量的时钟周期进行计数,提供延迟睡眠控制信号,并且基于对预定数量的环形振荡器周期进行计数来保持延迟的睡眠控制信号 到虚拟电源线电压。
    • 6. 发明授权
    • Fuse construction for integrated circuit structure having low dielectric constant dielectric material
    • 具有低介电常数介电材料的集成电路结构的保险丝结构
    • US06806551B2
    • 2004-10-19
    • US10376401
    • 2003-02-28
    • Yauh-Ching LiuRuggero CastagnettiRamnath Venkatraman
    • Yauh-Ching LiuRuggero CastagnettiRamnath Venkatraman
    • H01L2900
    • H01L23/5258H01L23/5329H01L2224/05022H01L2924/01019
    • Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
    • 保险丝和可选的金属焊盘形成在低k电介质材料结构的层上,其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。 电介质层形成在低k电介质材料上方和金属互连之上,并被图案化以形成其中与金属互连连通的第二开口。 导电阻挡层形成在与金属互连件接触的该电介质层上,并被图案化以在一些金属互连件之间形成熔丝部分,以及在一个或多个金属互连件上的衬垫。 然后在图案化的导电阻挡层上方形成电介质层,以形成每个保险丝上方的窗口,并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。
    • 7. 发明授权
    • High density memory with storage capacitor
    • 具有存储电容器的高密度存储器
    • US06687114B1
    • 2004-02-03
    • US10403433
    • 2003-03-31
    • Arvind KamathRuggero Castagnetti
    • Arvind KamathRuggero Castagnetti
    • H01G4228
    • H01L27/1087H01L27/10894H01L29/66181
    • A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.
    • 具有在硅衬底中形成的晶体管和电容器的存储单元。 电容器形成有在硅衬底的投影表面区域中蚀刻的下导电板。 下导电板具有至少一个vee形状的横截面,其中,vee的侧面与硅衬底的顶表面成约五十五度的角度。 下导电板的表面积比其中蚀刻下导电板的硅衬底的投影表面积大约百分之七点三。 电容器介电层由邻近下导电板设置的第一沉积介电层形成。 顶部导电板设置在电容器电介质层附近并与下部导电板相对。 晶体管形成为具有由沟道区域分离的源极和漏极区域以及由第一沉积介电层形成的栅极电介质层。
    • 8. 发明授权
    • Fuse construction for integrated circuit structure having low dielectric constant dielectric material
    • 具有低介电常数介电材料的集成电路结构的保险丝结构
    • US06566171B1
    • 2003-05-20
    • US09882404
    • 2001-06-12
    • Yauh-Ching LiuRuggero CastagnettiRamnath Venkatraman
    • Yauh-Ching LiuRuggero CastagnettiRamnath Venkatraman
    • H01L2182
    • H01L23/5258H01L23/5329H01L2224/05022H01L2924/01019
    • Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
    • 保险丝和可选的金属焊盘形成在低k电介质材料结构的层上,其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。 电介质层形成在低k电介质材料上方和金属互连之上,并被图案化以形成其中与金属互连连通的第二开口。 导电阻挡层形成在与金属互连件接触的该电介质层上,并被图案化以在一些金属互连件之间形成熔丝部分,以及在一个或多个金属互连件上的衬垫。 然后在图案化的导电阻挡层上方形成电介质层,以形成每个保险丝上方的窗口,并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。