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    • 1. 发明授权
    • Method and system for providing a sense amplifier and drive circuit for spin transfer torque magnetic random access memory
    • 提供感应放大器和驱动电路的自动转移转矩磁性随机存取存储器的方法和系统
    • US07764536B2
    • 2010-07-27
    • US11834917
    • 2007-08-07
    • Xiao LuoDavid Chang-Cheng Yu
    • Xiao LuoDavid Chang-Cheng Yu
    • G11C11/00
    • G11C11/1673G11C11/1659
    • A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disables at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.
    • 描述了一种用于提供磁存储器的方法和系统。 该方法和系统包括多个磁存储单元,多个位线,至少一个参考线和至少一个读出放大器。 每个磁存储单元包括磁性元件和选择装置。 磁性元件可通过驱动通过磁性元件的写入电流来编程。 位线和源极线对应于磁存储单元。 读出放大器与位线和参考线耦合,并且包括逻辑和多个级。 阶段包括第一和第二阶段。 第一级至少将电流信号转换为至少一个差分电压信号。 第二级放大至少一个差分电压信号。 在没有读取操作的情况下,逻辑选择性地禁用第一和第二级中的至少一个,并且在读取操作期间启用第一级和第二级。
    • 4. 发明申请
    • METHOD AND SYSTEM FOR PROVIDING A SENSE AMPLIFIER AND DRIVE CIRCUIT FOR SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY
    • 用于提供感测放大器和驱动电路的方法和系统,用于旋转转矩磁性随机存取存储器
    • US20090040855A1
    • 2009-02-12
    • US11834917
    • 2007-08-07
    • Xiao LuoDavid Chang-Cheng Yu
    • Xiao LuoDavid Chang-Cheng Yu
    • G11C7/00G11C11/06
    • G11C11/1673G11C11/1659
    • A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disablies at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.
    • 描述了一种用于提供磁存储器的方法和系统。 该方法和系统包括多个磁存储单元,多个位线,至少一个参考线和至少一个读出放大器。 每个磁存储单元包括磁性元件和选择装置。 磁性元件可通过驱动通过磁性元件的写入电流来编程。 位线和源极线对应于磁存储单元。 读出放大器与位线和参考线耦合,并且包括逻辑和多个级。 阶段包括第一和第二阶段。 第一级至少将电流信号转换为至少一个差分电压信号。 第二级放大至少一个差分电压信号。 在没有读取操作的情况下,逻辑选择性地抵消第一级和第二级中的至少一级,并且在读取操作期间启用第一级和第二级。
    • 5. 发明授权
    • Bi-directional data bus scheme with optimized read and write characters
    • 具有优化读写字符的双向数据总线方案
    • US6134153A
    • 2000-10-17
    • US364181
    • 1999-07-29
    • Valerie LinesCynthia MarXiao LuoSampei Miyamoto
    • Valerie LinesCynthia MarXiao LuoSampei Miyamoto
    • G11C7/10G11C7/00G11C8/00
    • G11C7/1051G11C7/1048
    • A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle. By implementing this scheme internally, a uniform read or write operating frequency is seen by the microprocessor, thereby simplifying its interface with the memory.
    • 提供了一种用于随机存取存储器的双向全局数据总线方案,其优化用于读取和写入操作的数据路径的性能,同时向外部处理器或控制器提供均匀的读取和写入频率。 该系统利用双局部数据总线结构,其允许列地址在每个时钟周期上改变,因为两个并行的本地数据路径在交替时钟周期上被激活,因此以标称工作频率的一半工作。 对于读操作,全局数据总线在标称工作频率下差分工作。 对于写入操作,全局数据总线以额定工作频率的一半工作,互补数据总线对的每个全局数据总线专用于每隔一个时钟周期的一个或另一个本地数据路径。 通过内部实现该方案,微处理器可以看到均匀的读或写操作频率,从而简化了与存储器的接口。
    • 6. 发明授权
    • Method and system for providing a magnetic memory structure utilizing spin transfer
    • 提供利用自旋转移的磁记忆体结构的方法和系统
    • US07623369B2
    • 2009-11-24
    • US12030541
    • 2008-02-13
    • Xiao LuoEugene ChenLien-Chang WangYiming Huai
    • Xiao LuoEugene ChenLien-Chang WangYiming Huai
    • G11C16/04
    • G11C11/1675G11C8/12G11C8/14G11C11/1657G11C11/1659G11C11/1673
    • A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element is programed by first and second write currents driven through the magnetic element in first and second directions. The local word lines are connected with the selection device of and have a first resistivity. Each global word line corresponds to a portion of the local word lines and has a resistivity lower than the first resistivity. The bit lines are connected with the magnetic element. The source lines are connected with the selection device. Each source line corresponds to a more than one of the magnetic memory cells and carries the first and second write currents.
    • 描述了一种用于提供磁存储器的方法和系统。 该方法和系统包括提供磁存储器单元,局部和全局字线,位线和源极线。 每个磁存储单元包括磁性元件和与该磁性元件连接的选择装置。 磁性元件由在第一和第二方向通过磁性元件驱动的第一和第二写入电流编程。 局部字线与第一电阻率的选择装置连接。 每个全局字线对应于局部字线的一部分,并具有低于第一电阻率的电阻率。 位线与磁性元件连接。 源极线与选择器件连接。 每个源极线对应于多个磁存储器单元并且承载第一和第二写入电流。
    • 8. 发明申请
    • Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells having enhanced read and write margins
    • 利用具有增强的读和写余量的这样的单元使用自旋转移和磁存储的磁存储单元的电流驱动切换
    • US20070297223A1
    • 2007-12-27
    • US11476171
    • 2006-06-26
    • Eugene Youjun ChenYiming HuaiAlex Fischer PanchulaLien-Chang WangXiao Luo
    • Eugene Youjun ChenYiming HuaiAlex Fischer PanchulaLien-Chang WangXiao Luo
    • G11C11/15
    • G11C11/16
    • A method and system for providing a magnetic memory is described. The magnetic memory includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. The magnetic element(s) are programmable by write currents driven through the magnetic element(s). Each magnetic element has free and pinned layer(s) and a dominant spacer. The magnetic memory is configured such that either the read current(s) flow from the free layer(s) to the dominant spacer if the maximum low resistance state read current divided by the minimum low resistance state write current is greater than the maximum high resistance state read current divided by the minimum high resistance state write current or the read current(s) flow from the dominant spacer to the free layer(s) if the maximum low resistance state read current divided by the minimum low resistance state write current is less than the maximum high resistance state read current divided by the minimum high resistance state write current.
    • 描述了一种用于提供磁存储器的方法和系统。 磁存储器包括阵列中的磁存储单元,位线和源极线。 每个磁存储单元包括至少一个磁性元件。 磁性元件可以通过驱动通过磁性元件的写入电流来编程。 每个磁性元件具有自由和固定的层和主要间隔物。 如果最大低电阻状态读取电流除以最小低电阻状态写入电流除以最大高电阻,则磁存储器被配置为使得读取电流从自由层流向主要间隔物 如果最小低电阻状态读取电流除以最小低电阻状态写入电流,则状态读取电流除以最小高电阻状态写入电流或从主要间隔物到自由层的读取电流(s) 比最大高电阻状态读取电流除以最小高电阻状态写入电流。