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1. 发明授权

US6134153A Bi-directional data bus scheme with optimized read and write characters 有权
标题翻译：具有优化读写字符的双向数据总线方案
公开(公告)号：US6134153A
公开(公告)日：2000-10-17
申请号：US364181
申请日：1999-07-29
申请人： Valerie Lines , Cynthia Mar , Xiao Luo , Sampei Miyamoto
发明人： Valerie Lines , Cynthia Mar , Xiao Luo , Sampei Miyamoto
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C7/1048
摘要： A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle. By implementing this scheme internally, a uniform read or write operating frequency is seen by the microprocessor, thereby simplifying its interface with the memory.
摘要翻译：提供了一种用于随机存取存储器的双向全局数据总线方案，其优化用于读取和写入操作的数据路径的性能，同时向外部处理器或控制器提供均匀的读取和写入频率。该系统利用双局部数据总线结构，其允许列地址在每个时钟周期上改变，因为两个并行的本地数据路径在交替时钟周期上被激活，因此以标称工作频率的一半工作。对于读操作，全局数据总线在标称工作频率下差分工作。对于写入操作，全局数据总线以额定工作频率的一半工作，互补数据总线对的每个全局数据总线专用于每隔一个时钟周期的一个或另一个本地数据路径。通过内部实现该方案，微处理器可以看到均匀的读或写操作频率，从而简化了与存储器的接口。

2. 发明授权

US5982674A Bi-directional data bus scheme with optimized read and write characters 有权
公开(公告)号：US5982674A
公开(公告)日：1999-11-09
申请号：US163341
申请日：1998-09-30
申请人： Valeria Lines , Cynthia Mar , Xiao Luo , Sampei Miyamoto
发明人： Valeria Lines , Cynthia Mar , Xiao Luo , Sampei Miyamoto
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C7/1048
摘要： A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle. By implementing this scheme internally, a uniform read or write operating frequency is seen by the microprocessor, thereby simplifying its interface with the memory.

3. 发明授权

US5394368A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5394368A
公开(公告)日：1995-02-28
申请号：US50231
申请日：1993-06-21
申请人： Sampei Miyamoto
发明人： Sampei Miyamoto
IPC分类号： G11C29/00 , G11C11/407
CPC分类号： G11C29/78 , G11C29/848
摘要： A semiconductor memory device having a redundancy circuit having a large flexibility, wherein a plurality of fuse columns are operated by address signals.
摘要翻译： PCT No.PCT / JP91 / 01142 Sec。 371日期：1993年6月21日 102（e）日期1993年6月21日PCT 1991年8月28日PCT PCT。第WO93 / 05512号公报日期1993年3月18日。一种具有灵活性大的冗余电路的半导体存储器件，其中多个熔丝列由地址信号操作。

4. 发明授权

US5521869A Semiconductor memory with improved transfer gate drivers 失效
公开(公告)号：US5521869A
公开(公告)日：1996-05-28
申请号：US351117
申请日：1994-11-30
申请人： Tamihiro Ishimura , Sampei Miyamoto
发明人： Tamihiro Ishimura , Sampei Miyamoto
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/407 , H03K3/356 , H03K17/10 , H03K19/017 , H03K17/06
CPC分类号： G11C7/06 , H03K17/102 , H03K3/356017 , H03K3/356113
摘要： A semiconductor memory has a sense amplifier array shared by first and second memory cell arrays, which are selected by first and second selection signals. Interconnections between the sense amplifier array and the first memory cell array are controlled by a first transfer gate signal. When the first selection signal is inactive, the second selection signal is coupled through a first transfer gate driver to become the first transfer gate signal. When the first selection signal is active, the first transfer gate signal is decoupled from the second selection signal and driven to an elevated level.

5. 发明授权

US4843258A Drive circuit with a ring oscillator for a semiconductor device 失效
标题翻译：具有用于半导体器件的环形振荡器的驱动电路
公开(公告)号：US4843258A
公开(公告)日：1989-06-27
申请号：US226087
申请日：1988-07-29
申请人： Masahumi Miyawaki , Sampei Miyamoto , Tamihiro Ishimura
发明人： Masahumi Miyawaki , Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G05F3/24 , G11C11/407 , G11C11/413 , H02M3/07 , H03K3/03 , H03K3/354
CPC分类号： G05F3/24 , H03K3/0315 , H03K3/354
摘要： A drive circuit for driving a semiconductor device includes a reference voltage level generator for outputting a reference voltage level which is associated with an input voltage level from an external power source. Supplied with the reference level, a ring oscillator oscillates a frequency signal having a predetermined frequency. A drive voltage level generator responds to the reference level and the frequency signal for producing a drive voltage level which is constantly substantially equal to the reference level in synchronism with the frequency signal. The drive voltage level generator feeds power from the external power source to the semiconductor device at the drive level, thereby driving the semiconductor load circuit.
摘要翻译：用于驱动半导体器件的驱动电路包括用于输出与来自外部电源的输入电压电平相关联的参考电压电平的参考电压电平发生器。提供参考电平，环形振荡器振荡具有预定频率的频率信号。驱动电压电平发生器响应参考电平和频率信号，以产生与频率信号同步地恒定地基本上等于参考电平的驱动电压电平。驱动电压电平发生器将来自外部电源的功率从驱动电平提供给半导体器件，由此驱动半导体负载电路。

6. 发明授权

US5818787A Semiconductor memory device 失效
公开(公告)号：US5818787A
公开(公告)日：1998-10-06
申请号：US833046
申请日：1997-04-03
申请人： Sampei Miyamoto , Tamihiro Ishimura
发明人： Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419 , G11C11/4096 , G11C7/1048
摘要： A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.

7. 发明授权

US5625315A Booster power generating circuit 失效
标题翻译：增压发电电路
公开(公告)号：US5625315A
公开(公告)日：1997-04-29
申请号：US529546
申请日：1995-09-18
申请人： Katsuaki Matsui , Sampei Miyamoto , Hidekazu Kikuchi
发明人： Katsuaki Matsui , Sampei Miyamoto , Hidekazu Kikuchi
IPC分类号： H02M3/07 , G05F1/10
CPC分类号： H02M3/073
摘要： A booster power generating circuit according to the present invention comprises first to fourth booster circuits for supplying first to fourth booster potentials to first to fourth nodes in response to first to fourth pulse signals, a first precharge circuit for precharging the first node when controlled by the fourth booster potential from the fourth node, a second precharge circuit for precharging the third node when controlled by the second booster potential from the second node and a first output circuit for outputting the first booster potential of the first node to an output node, whereby a given booster potential can be output since there is no voltage drop of the boosted potential of the second and fourth nodes, there is obtained high potential between the first and third precharge circuits and the precharging speed of the first and third node is not slowed.
摘要翻译：根据本发明的升压功率发生电路包括：第一至第四升压电路，用于响应于第一至第四脉冲信号向第一至第四节点提供第一至第四升压电位;第一预充电电路，用于当由第四增强电位，第二预充电电路，用于当由第二节点由第二升压电位控制时预充电第三节点;以及第一输出电路，用于将第一节点的第一升压电位输出到输出节点，由此，由于第二和第四节点的升压电位没有电压降，所以能够输出给定的升压电位，所以在第一和第三预充电电路之间获得高电位，并且第一和第三节点的预充电速度不会降低。

8. 发明授权

US5394374A Semiconductor memory with improved transfer gate drivers 失效
标题翻译：具有改进的传输栅极驱动器的半导体存储器
公开(公告)号：US5394374A
公开(公告)日：1995-02-28
申请号：US25677
申请日：1993-03-03
申请人： Tamihiro Ishimura , Sampei Miyamoto
发明人： Tamihiro Ishimura , Sampei Miyamoto
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/407 , H03K3/356 , H03K17/10 , H03K19/017 , H03K17/06
CPC分类号： G11C7/06 , H03K17/102 , H03K3/356017 , H03K3/356113
摘要： A semiconductor memory has a sense amplifier array shared by first and second memory cell arrays, which are selected by first and second selection signals. Interconnections between the sense amplifier array and the first memory cell array are controlled by a first transfer gate signal. When the first selection signal is inactive, the second selection signal is coupled through a first transfer gate driver to become the first transfer gate signal. When the first selection signal is active, the first transfer gate signal is decoupled from the second selection signal and driven to an elevated level.
摘要翻译：半导体存储器具有通过第一和第二选择信号选择的第一和第二存储单元阵列共享的读出放大器阵列。读出放大器阵列和第一存储单元阵列之间的互连由第一传输门信号控制。当第一选择信号无效时，第二选择信号通过第一传输门驱动器耦合成为第一传输门信号。当第一选择信号有效时，第一传输门信号与第二选择信号解耦并被驱动到升高的电平。

9. 发明申请

US20080284504A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20080284504A1
公开(公告)日：2008-11-20
申请号：US12140351
申请日：2008-06-17
申请人： Makoto Hirota , Hidekazu Kikuchi , Sampei Miyamoto
发明人： Makoto Hirota , Hidekazu Kikuchi , Sampei Miyamoto
IPC分类号： G05F3/16
CPC分类号： H03K19/0016
摘要： This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field effect transistor, to the first field effect transistor during the operation mode of the first circuit, and applies a second source bias voltage, which reversely biases between the source and the body of the first field effect transistor, to the first field effect transistor during the standby mode of the first circuit. During the standby mode of the first circuit, the leakage current that flows through the first FET is reduced by means of the reverse bias effect produced by applying the second source bias voltage to the source of the first FET.
摘要翻译：该器件具有包括耦合到第一电场晶体管的源极的第一场效应晶体管和第二电路的第一电路。第二电路在第一电路的操作模式期间施加第一源极偏置电压，其不在第一场效应晶体管的源极和本体之间反向偏置到第一场效应晶体管，并施加第二源极偏置电压，其在第一电路的待机模式期间将第一场效应晶体管的源极和主体之间的偏置反向偏移到第一场效应晶体管。在第一电路的待机模式期间，通过将第二源偏置电压施加到第一FET的源而产生的反向偏置效应，流过第一FET的漏电流减小。

10. 发明授权

US5850362A Semiconductor memory device employing an improved layout of sense amplifiers 失效
标题翻译：采用改进的读出放大器布局的半导体存储器件
公开(公告)号：US5850362A
公开(公告)日：1998-12-15
申请号：US619418
申请日：1996-03-21
申请人： Shinzo Sakuma , Sampei Miyamoto
发明人： Shinzo Sakuma , Sampei Miyamoto
IPC分类号： G11C11/409 , G11C5/06 , G11C7/00 , G11C11/401 , G11C11/4091 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C11/4097 , G11C11/4091
摘要： A memory device according to the invention has a first pair of bit lines, having first and second bit lines, coupled to a first memory cell which cause a first potential difference between the first and second bit lines; a second pair of bit lines, having third and fourth bit lines, coupled to a second memory cell which causes a second potential difference between the third and fourth bit lines; a first sense amplifier having first and second transistors each of which is a first conductivity type, the gate electrode of said first transistor being connected to said first bit line, the first electrode of the first transistor being connected to the second bit line, the gate electrode of the second transistor being connected to the second bit line, the first electrode of the second transistor being connected to the first bit line; a second sense amplifier having third and fourth transistors each of which is the first conductivity type, the gate electrode of the third transistor being connected to the third bit line, the first electrode of the third transistor being connected to the fourth bit line, the gate electrode of the fourth transistor being connected to the fourth bit line, the first electrode of the fourth transistor being connected to the third bit line; and the second electrodes of said first, second, third and fourth transistors constituting a first common diffusion region formed in a first area of the major surface.
摘要翻译：根据本发明的存储器件具有第一对位线，其具有第一和第二位线，耦合到第一存储器单元，该第一存储器单元引起第一和第二位线之间的第一电位差; 具有第三和第四位线的第二对位线，耦合到第二存储器单元，所述第二存储单元引起所述第三和第四位线之间的第二电位差; 具有第一和第二晶体管的第一感测放大器，每个第一和第二晶体管都是第一导电类型，所述第一晶体管的栅电极连接到所述第一位线，第一晶体管的第一电极连接到第二位线，栅极第二晶体管的电极连接到第二位线，第二晶体管的第一电极连接到第一位线; 具有第三和第四晶体管的第二感测放大器，每个第三和第四晶体管是第一导电类型，第三晶体管的栅电极连接到第三位线，第三晶体管的第一电极连接到第四位线，栅极第四晶体管的电极连接到第四位线，第四晶体管的第一电极连接到第三位线; 并且所述第一，第二，第三和第四晶体管的第二电极构成形成在主表面的第一区域中的第一公共扩散区域。

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