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    • 6. 发明授权
    • High-rate interpolation or decimation filter in integrated circuit device
    • 集成电路设备中的高速内插或抽取滤波器
    • US08650236B1
    • 2014-02-11
    • US12535133
    • 2009-08-04
    • Shin-I Chou
    • Shin-I Chou
    • G06F17/17G06F17/10
    • H03H17/0621H03H17/0275H03H2017/0247H03H2017/0298
    • On a device having a maximum data rate, an interpolation filter can be configured in stages, with each stage may be broken into subfilters, which divides the output into phases. The ratio of the number of subfilters or phases in the final stage to the number of subfilters or phases in the initial stage is equal to the factor by which the data rate would otherwise increase. Thus for an interpolation factor of M, the output data rate can be kept the same as the input data rate by providing M subfilters, yielding M output phases each having an output rate equal to the input rate. The effective, or synthesized, output rate is M times the input rate. A decimation filter can be provided in the same way, with the effective input rate M times the output rate, even where the effective input rate would exceed the maximum data rate.
    • 在具有最大数据速率的设备上,可以分阶段地配置内插滤波器,其中每个级可以被分成子滤波器,其将输出分为相。 最后阶段的子过滤器或相位的数量与初始阶段中的子过滤器或相位的数量之比等于数据速率否则会增加的因素。 因此,对于M的内插因子,通过提供M个子滤波器,输出数据速率可以保持与输入数据速率相同,产生每个具有等于输入速率的输出速率的M个输出相位。 有效或合成的输出速率是输入速率的M倍。 即使在有效输入速率超过最大数据速率的情况下,可以以相同的方式提供抽取滤波器,有效输入速率为输出速率的M倍。
    • 8. 发明授权
    • Multi-rate filter bank
    • 多速率滤波器组
    • US08380772B2
    • 2013-02-19
    • US12637771
    • 2009-12-15
    • Kung-Piao Huang
    • Kung-Piao Huang
    • G06F17/10
    • H03H17/0294H03H17/0223H03H17/0621H03H2218/085
    • A multi-rate filter bank including an anti-aliasing filter, a plurality of multiplier block modules, a folding block, and a data composer is disclosed. The anti-aliasing filter receives an anti-aliasing input signal. The multiplier block modules receive an original signal and sequentially generate a plurality of processed signals. The multiplier block modules also receive a plurality of block input signals and a select signal. Each of the multiplier block modules is configured into a decimation block or an expanding anti-aliasing filter according to the select signal. The folding block receives the select signal and a folding input signal and generates a folding block output signal. The data composer receives and composes the folding block output signal and the outputs of the multiplexer block modules and the anti-aliasing filter and generates an anti-aliasing filter output signal.
    • 公开了一种包括抗混叠滤波器,多个乘法器模块,折叠块和数据编辑器的多速率滤波器组。 抗混叠滤波器接收抗混叠输入信号。 乘法器模块模块接收原始信号并顺序产生多个处理的信号。 乘法器模块还接收多个块输入信号和选择信号。 每个乘法器块模块根据选择信号配置成抽取块或扩展抗混叠滤波器。 折叠块接收选择信号和折叠输入信号,并产生折叠块输出信号。 数据编辑器接收和组合折叠块输出信号和多路复用器模块和抗混叠滤波器的输出,并产生抗混叠滤波器输出信号。
    • 10. 发明授权
    • Dither methods for suppression of data-dependent activity variations
    • 用于抑制数据依赖性活动变化的抖动方法
    • US07626721B2
    • 2009-12-01
    • US11546791
    • 2006-10-12
    • George S. MooreFrank Van de Sande
    • George S. MooreFrank Van de Sande
    • G06K1/00G06K15/02G06F15/00
    • H03H17/0621H03H17/0219
    • A system and method are provided for minimizing data-dependent power variations. The system and method can include summing an input with a dither signal, processing the summed signal, and substantially removing the effects of the dither signal from the output. The output is an approximation of processing to the input alone, while certain aspects of processing activity, such as temperature changes and current draw, are less dependent on input values. Variations in data-dependent activities are thus reduced. The effects of the dither signal may be removed by equivalently processing the dither signal alone, and using that result as a compensating signal to cancel components of the processed signal that result from the presence of the dither signal.
    • 提供了一种用于最小化依赖于数据的功率变化的系统和方法。 该系统和方法可以包括将输入与抖动信号相加,处理相加的信号,以及基本上去除抖动信号对输出的影响。 输出是对输入单独处理的近似值,而处理活动的某些方面(如温度变化和电流消耗)较少依赖于输入值。 因此,数据依赖活动的变化减少了。 可以通过等效地处理抖动信号来消除抖动信号的影响,并且使用该结果作为补偿信号来消除由抖动信号的存在引起的处理信号的分量。