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1. 发明申请

US20060267084A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060267084A1
公开(公告)日：2006-11-30
申请号：US11139976
申请日：2005-05-31
申请人： Wolfgang Rosner , Franz Hofmann , Michael Specht , Martin Stadele , Johannes Luyken
发明人： Wolfgang Rosner , Franz Hofmann , Michael Specht , Martin Stadele , Johannes Luyken
IPC分类号： H01L29/76
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7393
摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.
摘要翻译：半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极具有栅极电介质层和栅电极的结构。所述栅极结构布置在所述漏极区域和所述源极区域之间。提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。

2. 发明申请

US20060267064A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20060267064A1
公开(公告)日：2006-11-30
申请号：US11139977
申请日：2005-05-31
申请人： Wolfgang Rosner , Franz Hofmann , Michael Specht , Martin Stadele
发明人： Wolfgang Rosner , Franz Hofmann , Michael Specht , Martin Stadele
IPC分类号： H01L29/94
CPC分类号： H01L27/10873 , H01L21/7624 , H01L27/10802 , H01L27/1087 , H01L29/66181 , H01L29/7841 , H01L29/945
摘要： The semiconductor memory device comprises a plurality of memory cells. Each memory cell comprises a respective transistor and a respective capacitor unit. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, the drain area and source area are embedded in the transistor body on a first surface of the transistor body, and a gate structure having a gate dielectric layer and a gate electrode, the gate structure is arranged between the drain area and the source area. An isolation trench is arranged adjacent to said transistor body, having a dielectric layer and a conductive material, wherein the isolation trench is at least partially filled with the conductive material. The conductive material is isolated by said dielectric layer from the transistor body. The capacitor unit is formed by the transistor body representing a first electrode and the conductive material representing the second electrode.
摘要翻译：半导体存储器件包括多个存储单元。每个存储单元包括相应的晶体管和相应的电容器单元。晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，漏极区域和源极区域嵌入在晶体管本体的第一表面上，并且栅极具有栅极介电层和栅电极的结构，栅极结构布置在漏极区域和源极区域之间。绝缘沟槽被布置成与所述晶体管本体相邻，具有电介质层和导电材料，其中隔离沟槽至少部分地被导电材料填充。导电材料通过所述介电层与晶体管本体隔离。电容器单元由表示第一电极的晶体管体和表示第二电极的导电材料形成。

3. 发明申请

US20050110088A1 Substrate and method for producing a substrate 有权
标题翻译：基板及其制造方法
公开(公告)号：US20050110088A1
公开(公告)日：2005-05-26
申请号：US10968846
申请日：2004-10-18
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
IPC分类号： H01L21/20 , H01L21/762 , H01L27/01
CPC分类号： H01L21/76254
摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.
摘要翻译：衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。在半导体层上形成晶体管。

4. 发明授权

US07611928B2 Method for producing a substrate 有权
标题翻译：制造基板的方法
公开(公告)号：US07611928B2
公开(公告)日：2009-11-03
申请号：US10968846
申请日：2004-10-18
申请人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
发明人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
IPC分类号： H01L21/00
CPC分类号： H01L21/76254
摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.
摘要翻译：衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。在半导体层上形成晶体管。

5. 发明申请

US20070096198A1 Non-volatile memory cells and method for fabricating non-volatile memory cells 审中-公开
标题翻译：非易失性存储单元和用于制造非易失性存储单元的方法
公开(公告)号：US20070096198A1
公开(公告)日：2007-05-03
申请号：US11262309
申请日：2005-10-28
申请人： Franz Hofmann , Johannes Luyken , Michael Specht , Wolfgang Rosner
发明人： Franz Hofmann , Johannes Luyken , Michael Specht , Wolfgang Rosner
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L29/40117 , H01L29/42352 , H01L29/785
摘要： The invention relates to non-volatile memory cells. Further, the invention relates to a method for fabricating non-volatile memory cells. Memory cells are formed on a semiconductor wafer having a protruding element with a top surface. A transistor is formed having a first part, a second part, and a third part. The first part includes a first junction region and a first charge trapping layer on the top surface. The second part includes a second junction region and charge trapping layer on the top surface. The third part has a gate electrode and a gate dielectric layer at least partially on sidewalls of the protruding element. The gate electrode contacts the first and second charge trapping layers.
摘要翻译：本发明涉及非易失性存储单元。此外，本发明涉及一种制造非易失性存储单元的方法。存储单元形成在具有顶表面的突出元件的半导体晶片上。晶体管形成有第一部分，第二部分和第三部分。第一部分包括顶表面上的第一接合区域和第一电荷俘获层。第二部分包括顶表面上的第二结区和电荷捕获层。第三部分至少部分地在突出元件的侧壁上具有栅极电极和栅极电介质层。栅电极接触第一和第二电荷捕获层。

6. 发明申请

US20050269617A1 Semi-conductor component with condensators buried in the substrate and insulated component layer thereof 有权
标题翻译：半导体部件与冷凝器埋在基板和绝缘部件层中
公开(公告)号：US20050269617A1
公开(公告)日：2005-12-08
申请号：US10523944
申请日：2003-09-13
申请人： Franz Hofmann , Volker Lehmann , Lothar Risoh , Wolfgang Rosner , Michael Specht
发明人： Franz Hofmann , Volker Lehmann , Lothar Risoh , Wolfgang Rosner , Michael Specht
IPC分类号： H01L21/02 , H01L21/334 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/94 , H01L29/76
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10832 , H01L27/10867 , H01L27/1203 , H01L28/82 , H01L29/66181 , H01L29/945
摘要： A semiconductor substrate and a semiconductor circuit formed therein and associated fabrication methods are provided. A multiplicity of depressions with a respective dielectric layer and a capacitor electrode are formed for realizing buried capacitors in a carrier substrate and an actual semiconductor component layer being insulated from the carrier substrate by an insulation layer.
摘要翻译：提供了一种形成在其中的半导体衬底和半导体电路及其制造方法。形成具有相应电介质层和电容器电极的多个凹陷，用于在载体衬底中实现埋入式电容器，并且通过绝缘层与实施方式的半导体组件层与载体衬底绝缘。

7. 发明申请

US20050139893A1 Non-volatile flash semiconductor memory and fabrication method 有权
标题翻译：非易失性闪存半导体存储器及其制造方法
公开(公告)号：US20050139893A1
公开(公告)日：2005-06-30
申请号：US10991345
申请日：2004-11-09
申请人： Franz Hofmann , Erhard Landgraf , Wolfgang Rosner , Michael Specht , Martin Staedele
发明人： Franz Hofmann , Erhard Landgraf , Wolfgang Rosner , Michael Specht , Martin Staedele
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L21/8242 , H01L29/76
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the fins, in order to form side wall transistors, and between the gate electrodes forms parts of a word line belonging to the corresponding fin.
摘要翻译：在半导体存储器中，在由半导体材料制成的翅片的相应顶侧上存在多个具有捕获层或浮栅电极作为存储介质的FinFET布置。栅电极的材料也存在于翅片的两个侧壁上，以便形成侧壁晶体管，并且在栅电极之间形成属于相应鳍片的字线的部分。

8. 发明申请

US20080054324A1 INTEGRATED CIRCUIT INCLUDING A GATE ELECTRODE 有权
标题翻译：集成电路，包括门电极
公开(公告)号：US20080054324A1
公开(公告)日：2008-03-06
申请号：US11926653
申请日：2007-10-29
申请人： Richard Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rosner , Till Schloesser , Michael Specht
发明人： Richard Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rosner , Till Schloesser , Michael Specht
IPC分类号： H01L29/94
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at at least two opposite sides.
摘要翻译：公开了一种包括栅电极的集成电路。一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。在半导体衬底中的第一和第二源极/漏极之间布置有沟道。栅电极被布置在沟道层附近并且与沟道层电绝缘。半导体基板电极设置在后侧。栅电极在至少两个相对的两侧包围沟道层。

9. 发明授权

US07157768B2 Non-volatile flash semiconductor memory and fabrication method 有权
标题翻译：非易失性闪存半导体存储器及其制造方法
公开(公告)号：US07157768B2
公开(公告)日：2007-01-02
申请号：US10991345
申请日：2004-11-09
申请人： Franz Hofmann , Erhard Landgraf , Wolfgang Rosner , Michael Specht , Martin Staedele
发明人： Franz Hofmann , Erhard Landgraf , Wolfgang Rosner , Michael Specht , Martin Staedele
IPC分类号： H01L27/115
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the fins, in order to form side wall transistors, and between the gate electrodes forms parts of a word line belonging to the corresponding fin.
摘要翻译：在半导体存储器中，在由半导体材料制成的翅片的相应顶侧上存在多个具有捕获层或浮栅电极作为存储介质的FinFET布置。栅电极的材料也存在于翅片的两个侧壁上，以便形成侧壁晶体管，并且在栅电极之间形成属于相应鳍片的字线的部分。

10. 发明申请

US20060011972A1 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权
标题翻译：非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法
公开(公告)号：US20060011972A1
公开(公告)日：2006-01-19
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
IPC分类号： H01L29/792
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译：公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入到电绝缘层中的电荷载流子的影响。

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