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1. 发明申请

US20070096198A1 Non-volatile memory cells and method for fabricating non-volatile memory cells 审中-公开
标题翻译：非易失性存储单元和用于制造非易失性存储单元的方法
公开(公告)号：US20070096198A1
公开(公告)日：2007-05-03
申请号：US11262309
申请日：2005-10-28
申请人： Franz Hofmann , Johannes Luyken , Michael Specht , Wolfgang Rosner
发明人： Franz Hofmann , Johannes Luyken , Michael Specht , Wolfgang Rosner
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L29/40117 , H01L29/42352 , H01L29/785
摘要： The invention relates to non-volatile memory cells. Further, the invention relates to a method for fabricating non-volatile memory cells. Memory cells are formed on a semiconductor wafer having a protruding element with a top surface. A transistor is formed having a first part, a second part, and a third part. The first part includes a first junction region and a first charge trapping layer on the top surface. The second part includes a second junction region and charge trapping layer on the top surface. The third part has a gate electrode and a gate dielectric layer at least partially on sidewalls of the protruding element. The gate electrode contacts the first and second charge trapping layers.
摘要翻译：本发明涉及非易失性存储单元。此外，本发明涉及一种制造非易失性存储单元的方法。存储单元形成在具有顶表面的突出元件的半导体晶片上。晶体管形成有第一部分，第二部分和第三部分。第一部分包括顶表面上的第一接合区域和第一电荷俘获层。第二部分包括顶表面上的第二结区和电荷捕获层。第三部分至少部分地在突出元件的侧壁上具有栅极电极和栅极电介质层。栅电极接触第一和第二电荷捕获层。

2. 发明申请

US20060128088A1 Vertical integrated component, component arrangement and method for production of a vertical integrated component 失效
标题翻译：垂直集成部件，组件布置和垂直集成部件生产方法
公开(公告)号：US20060128088A1
公开(公告)日：2006-06-15
申请号：US10533550
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Luyken , Wolfgang Rosner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Luyken , Wolfgang Rosner , Thomas Schulz , Michael Specht
IPC分类号： H01L21/8238
CPC分类号： H01L29/78642 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66742 , H01L29/66787 , H01L29/775 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.
摘要翻译：本发明涉及垂直集成部件，部件布置和用于生产垂直集成部件的方法。垂直集成部件具有第一导电层，中间层，其部分地由第一导电层上的介电材料实现，中间层上的第二导电层和集成在中间层中的贯通保持件中的纳米结构。纳米结构的第一端部分耦合到第一导电层，第二端部分耦合到第二导电层。中间层包括在两个相邻的介电部分层之间的第三导电层，其厚度小于介电部分层中的至少一个的厚度。

3. 发明申请

US20060267084A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060267084A1
公开(公告)日：2006-11-30
申请号：US11139976
申请日：2005-05-31
申请人： Wolfgang Rosner , Franz Hofmann , Michael Specht , Martin Stadele , Johannes Luyken
发明人： Wolfgang Rosner , Franz Hofmann , Michael Specht , Martin Stadele , Johannes Luyken
IPC分类号： H01L29/76
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7393
摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.
摘要翻译：半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极具有栅极电介质层和栅电极的结构。所述栅极结构布置在所述漏极区域和所述源极区域之间。提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。

4. 发明授权

US07829892B2 Integrated circuit including a gate electrode 有权
标题翻译：集成电路包括栅电极
公开(公告)号：US07829892B2
公开(公告)日：2010-11-09
申请号：US11926653
申请日：2007-10-29
申请人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
发明人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
IPC分类号： H01L29/12
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.
摘要翻译：公开了一种包括栅电极的集成电路。一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。在半导体衬底中的第一和第二源极/漏极之间布置有沟道。栅电极被布置在沟道层附近并且与沟道层电绝缘。半导体基板电极设置在后侧。栅极电极将沟道层包围至少两个相对的侧面。

5. 发明授权

US07611928B2 Method for producing a substrate 有权
标题翻译：制造基板的方法
公开(公告)号：US07611928B2
公开(公告)日：2009-11-03
申请号：US10968846
申请日：2004-10-18
申请人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
发明人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
IPC分类号： H01L21/00
CPC分类号： H01L21/76254
摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.
摘要翻译：衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。在半导体层上形成晶体管。

6. 发明授权

US07598543B2 Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration 失效
标题翻译：具有存储单元体区域的半导体存储器组件具有凹陷和渐变的掺杂剂浓度
公开(公告)号：US07598543B2
公开(公告)日：2009-10-06
申请号：US11438883
申请日：2006-05-23
申请人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Staedele
发明人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Staedele
IPC分类号： H01L27/108
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203
摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.
摘要翻译：半导体存储器组件包括至少一个存储单元。存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。

7. 发明授权

US07335939B2 Semiconductor memory device and method of production 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07335939B2
公开(公告)日：2008-02-26
申请号：US11135002
申请日：2005-05-23
申请人： Franz Hofmann , Johannes Luyken , Michael Specht
发明人： Franz Hofmann , Johannes Luyken , Michael Specht
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4232 , H01L29/42352 , H01L29/66833
摘要： An array of charge-trapping memory cells and pluralities of parallel wordlines and parallel bitlines running transversely to the wordlines are arranged on a substrate surface. Gate electrodes are located between the wordlines and bitlines and are, in their sequence along the direction of the wordlines, connected alternatingly to one of two adjacent wordlines.
摘要翻译：电荷俘获存储器单元阵列和横向于字线的并行字线和并行位线的多个排列在衬底表面上。栅电极位于字线和位线之间，并且沿着字线方向的顺序交替地连接到两个相邻字线之一。

8. 发明授权

US07265376B2 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权
标题翻译：非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法
公开(公告)号：US07265376B2
公开(公告)日：2007-09-04
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L35/24 , H01L51/00 , H01L29/788 , H01L21/336
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译：公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入电绝缘层中的电荷载流子的影响。

9. 发明授权

US07208794B2 High-density NROM-FINFET 失效
标题翻译：高密度NROM-FINFET
公开(公告)号：US07208794B2
公开(公告)日：2007-04-24
申请号：US11073017
申请日：2005-03-04
申请人： Franz Hofmann , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/119
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , Y10S257/903 , Y10S257/904 , Y10S257/905
摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.
摘要翻译：具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中，肋骨肋具有基本上矩形的形状，肋的上侧和肋侧面相对。存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。

10. 发明申请

US20070018201A1 Non-volatile memory cells and methods for fabricating non-volatile memory cells 有权
标题翻译：非易失性存储单元和用于制造非易失性存储单元的方法
公开(公告)号：US20070018201A1
公开(公告)日：2007-01-25
申请号：US11187693
申请日：2005-07-22
申请人： Michael Specht , Franz Hofmann , Johannes Luyken
发明人： Michael Specht , Franz Hofmann , Johannes Luyken
IPC分类号： H01L27/10
CPC分类号： H01L27/11568 , H01L21/84 , H01L27/115 , H01L27/1203 , H01L29/785
摘要： The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a bulk semi-conductive substrate and an SOI semi-conductive layer and are arranged as a bulk FinFET transistor and an SOI FinFet transistor being arranged on top of the bulk FinFET transistor. Both the FinFET transistor and the SOI FinFet transistor are attached to a common charge-trapping layer. A word line with sidewalls is arranged on top of said patterned charge-trapping layer and a spacer oxide layer is arranged on the sidewalls of said word line.
摘要翻译：本发明涉及一种用于制造堆叠的非易失性存储单元的方法。此外，本发明涉及堆叠的非易失性存储单元。本发明特别涉及具有非易失性堆叠存储单元的非易失性NAND存储器的领域。层叠的非易失性存储单元形成在具有体半导体基板和SOI半导电层的半导体晶片上，并且被布置为体FinFET晶体管，并且SOI FinFet晶体管布置在体FinFET晶体管的顶部。 FinFET晶体管和SOI FinFet晶体管都连接到公共的电荷俘获层。具有侧壁的字线被布置在所述图案化的电荷捕获层的顶部上，并且间隔氧化物层被布置在所述字线的侧壁上。

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