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1. 发明授权

US06867130B1 Enhanced silicidation of polysilicon gate electrodes 有权
标题翻译：增强多晶硅栅电极的硅化
公开(公告)号：US06867130B1
公开(公告)日：2005-03-15
申请号：US10445936
申请日：2003-05-28
申请人： Olov B. Karlsson , Simon S. Chan , William G. En , Mark W. Michael
发明人： Olov B. Karlsson , Simon S. Chan , William G. En , Mark W. Michael
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66507 , H01L21/28114 , H01L21/28518 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes. Embodiments include forming the thin metal silicide layers on the polysilicon gate electrodes and source/drain regions, depositing a dielectric gap filling layer, as by high density plasma deposition, etching back to selectively expose the silicidized polysilicon gate electrodes and resilicidizing the polysilicon gate electrodes to increase the thickness of the metal silicide layers thereon. Embodiments further include resilicidizing the polysilicon gate electrodes including a portion of the upper side surfaces forming mushroom shaped metal silicide layers.
摘要翻译：通过在栅极电极和源极/漏极区域上形成薄金属硅化物层，然后选择性地使栅电极重新硅化，来制造在源极/漏极区域中显示出降低的栅极电阻和减少的硅化物尖峰的半导体器件。实施例包括在多晶硅栅极电极和源极/漏极区域上形成薄金属硅化物层，通过高密度等离子体沉积沉积介电间隙填充层，回蚀刻以选择性地暴露硅化多晶硅栅电极并使多晶硅栅电极重新硅化增加其上的金属硅化物层的厚度。实施例还包括重新硅化多晶硅栅电极，其包括形成蘑菇状金属硅化物层的上侧表面的一部分。

2. 发明授权

US08314454B2 Local interconnect having increased misalignment tolerance 有权
公开(公告)号：US08314454B2
公开(公告)日：2012-11-20
申请号：US12970687
申请日：2010-12-16
申请人： Simon S. Chan
发明人： Simon S. Chan
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

3. 发明授权

US07144818B2 Semiconductor substrate and processes therefor 有权
标题翻译：半导体衬底及其工艺
公开(公告)号：US07144818B2
公开(公告)日：2006-12-05
申请号：US10729479
申请日：2003-12-05
申请人： Mario M. Pelella , Simon S. Chan
发明人： Mario M. Pelella , Simon S. Chan
IPC分类号： H01L21/311
CPC分类号： H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/3043 , H01L29/7842
摘要： A method of manufacturing an integrated circuit (IC) can utilizes semiconductor substrate configured in accordance with a trench process. The substrate utilizes trenches in a base layer to induce stress in a layer. The substrate can include silicon. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.
摘要翻译：集成电路（IC）的制造方法可以利用根据沟槽工艺配置的半导体衬底。衬底利用基层中的沟槽以在层中引起应力。衬底可以包括硅。沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

4. 发明授权

US06291339B1 Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same 有权
标题翻译：双层层间电介质具有在不同密度的图案特征上具有基本上均匀的复合层间介电常数的方法，以及制造其的方法
公开(公告)号：US06291339B1
公开(公告)日：2001-09-18
申请号：US09225218
申请日：1999-01-04
申请人： Steven C. Avanzino , Simon S. Chan
发明人： Steven C. Avanzino , Simon S. Chan
IPC分类号： H01L214263
CPC分类号： H01L21/76819
摘要： A bilayer interlayer dielectric having a spun-on low k gap filled layer is capped with a higher k dielectric layer. Prior to the capping, the spun-on low k dielectric layer is planarized to reduce or eliminate the systematic variation in the relative thickness of the layers due to pattern density effects on the thickness of the spun-on low k dielectric layer. By removing the variations in the relative thickness of the low k dielectric layer and the capping layer, the effective dielectric constant of the uniformly thick composite interlayer dielectric is independent of location on the circuit, preventing differences in circuit speed and the creation of clock skew in the circuit.
摘要翻译：具有旋转低k间隙填充层的双层层间电介质用较高的k电介质层封装。在封盖之前，由于图案密度对纺丝低k电介质层的厚度的影响，使旋转低k电介质层平坦化以减少或消除层的相对厚度的系统变化。通过去除低k电介质层和覆盖层的相对厚度的变化，均匀厚的复合层间电介质的有效介电常数与电路上的位置无关，防止电路速度的差异和时钟偏差的产生电路。

5. 发明授权

US6093635A High integrity borderless vias with HSQ gap filled patterned conductive layers 失效
标题翻译：高完整性无边界通孔与HSQ间隙填充图案导电层
公开(公告)号：US6093635A
公开(公告)日：2000-07-25
申请号：US993124
申请日：1997-12-18
申请人： Khanh Tran , Richard J. Huang , Simon S. Chan , Lu You
发明人： Khanh Tran , Richard J. Huang , Simon S. Chan , Lu You
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/3105 , H01L21/76814 , H01L21/76826 , H01L21/76828 , Y10S438/958
摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.
摘要翻译：无边界通孔形成为与填充有HSQ的金属图案间隙的下部金属特征电连接。在填充通孔之前，在惰性气氛中进行热处理，以排出在通孔的溶剂清洗期间吸收的水，从而通过空隙形成和通过完整性改善。

6. 发明授权

US4808273A Method of forming completely metallized via holes in semiconductors 失效
标题翻译：在半导体中形成完全金属化的通孔的方法
公开(公告)号：US4808273A
公开(公告)日：1989-02-28
申请号：US192343
申请日：1988-05-10
申请人： Chang-Hwang Hua , Ding-Yuan S. Day , Simon S. Chan
发明人： Chang-Hwang Hua , Ding-Yuan S. Day , Simon S. Chan
IPC分类号： H01L21/74 , H01L21/768 , C25D5/02
CPC分类号： H01L21/76898
摘要： A method is disclosed for forming completely metallized via holes in semiconductor wafers. Metal pads are formed on one face of a semiconductor wafer together with a conductive interconnecting network. An insulating layer is then deposited to cover this face of the wafer. Holes are etched in the opposite face of the wafer up to and exposing a portion of the metal pads. The via holes are then completely filled with metal by means of electroplating, using the metal pads as a cathode.
摘要翻译：公开了一种用于在半导体晶片中形成完全金属化的通孔的方法。金属焊盘与导电互连网络一起形成在半导体晶片的一个面上。然后沉积绝缘层以覆盖晶片的这个面。孔在晶片的相对表面被蚀刻，直至并暴露出金属焊盘的一部分。然后使用金属垫作为阴极，通过电镀将通孔用金属完全填充。

7. 发明授权

US07879718B2 Local interconnect having increased misalignment tolerance 有权
标题翻译：本地互连具有增加的不对准公差
公开(公告)号：US07879718B2
公开(公告)日：2011-02-01
申请号：US11616544
申请日：2006-12-27
申请人： Simon S. Chan
发明人： Simon S. Chan
IPC分类号： H01L21/44
CPC分类号： H01L27/11568 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.
摘要翻译：提供一种用于在半导体存储器件中形成互连的方法。该方法包括在衬底上形成一对源极选择晶体管。源区域形成在一对源极选择晶体管之间的衬底中。在所述一对源极选择晶体管之间形成第一层间电介质。掩模层沉积在一对源极选择晶体管和层间电介质上，其中掩模层限定了一对源极选择晶体管之间的局部互连区域，其宽度小于一对源选择晶体管之间的距离。蚀刻半导体存储器件以去除局部互连区域中的第一层间电介质的一部分，从而暴露源极区域。在局部互连区域中形成金属接触。

8. 发明授权

US07538383B1 Two-bit memory cell having conductive charge storage segments and method for fabricating same 有权
标题翻译：具有导电电荷存储段的二位存储单元及其制造方法
公开(公告)号：US07538383B1
公开(公告)日：2009-05-26
申请号：US11416703
申请日：2006-05-03
申请人： Meng Ding , Simon S. Chan
发明人： Meng Ding , Simon S. Chan
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568
摘要： According to one exemplary embodiment, a two-bit memory cell includes a gate stack situated over a substrate, where the gate stack includes a charge-trapping layer. The charge-trapping layer includes first and second conductive segments and a nitride segment, where the nitride segment is situated between the first and second conductive segments. The nitride segment electrically insulates the first conductive segment from the second conductive segment. The first and second conductive segments provide respective first and second data bit storage locations in the two-bit memory cell. The gate stack can further include a lower oxide segment situated between the substrate and the charge-trapping layer. The gate stack can further include an upper oxide segment situated over the charge-trapping layer. The gate stack can be situated between a first dielectric segment and a second dielectric segment, where the first and second dielectric segments are situated over respective first and second bitlines.
摘要翻译：根据一个示例性实施例，两比特存储器单元包括位于衬底上方的栅极堆叠，其中栅极堆叠包括电荷捕获层。电荷捕获层包括第一和第二导电段和氮化物区段，其中氮化物区段位于第一和第二导电区段之间。氮化物区段将第一导电段与第二导电段电绝缘。第一和第二导电段在双位存储单元中提供相应的第一和第二数据位存储单元。栅极堆叠还可以包括位于衬底和电荷俘获层之间的较低氧化物段。栅极堆叠还可以包括位于电荷捕获层上方的上部氧化物段。栅极堆叠可以位于第一介电段和第二介电段之间，其中第一和第二介电段位于相应的第一和第二位线之上。

9. 发明授权

US07498222B1 Enhanced etching of a high dielectric constant layer 有权
标题翻译：增强蚀刻高介电常数层
公开(公告)号：US07498222B1
公开(公告)日：2009-03-03
申请号：US11371024
申请日：2006-03-09
申请人： John C. Foster , Scott Bell , Allison Holbrook , Simon S. Chan , Phillip Jones
发明人： John C. Foster , Scott Bell , Allison Holbrook , Simon S. Chan , Phillip Jones
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L29/513 , H01L29/66833
摘要： A high K layer, such as aluminum oxide or hafnium oxide, may be formed with a deposition process that uses an ion implantation to damage portions of the high K material that are to be later etched. More particularly, in one implementation, a semiconductor device is manufactured by forming a first dielectric over a substrate, forming a charge storage element over the first dielectric, forming a second dielectric above the charge storage element, implantation ions into select portions of the second dielectric, and etching the ion implanted select portions of the second dielectric.
摘要翻译：可以用沉积工艺形成高K层，例如氧化铝或氧化铪，所述沉积工艺使用离子注入来破坏将被蚀刻的高K材料的部分。更具体地，在一个实施方式中，通过在衬底上形成第一电介质来形成半导体器件，在第一电介质上形成电荷存储元件，在电荷存储元件上形成第二电介质，将离子注入第二电介质的选择部分并蚀刻第二电介质的离子注入选择部分。

10. 发明授权

US06518173B1 Method for avoiding fluorine contamination of copper interconnects 有权
标题翻译：避免铜互连的氟污染的方法
公开(公告)号：US06518173B1
公开(公告)日：2003-02-11
申请号：US09640081
申请日：2000-08-17
申请人： Simon S. Chan
发明人： Simon S. Chan
IPC分类号： H01L214763
CPC分类号： H01L21/31111 , H01L21/31116 , H01L21/76802
摘要： Corrosion and degradation of tantalum-based adhesion/barrier layers used in multi-level semiconductor devices employing copper-based interconnect metallization systems are avoided or minimized. In embodiments of the present invention, deleterious fluorine-containing contaminants formed on underlying copper-based metal features as a result of etching through-holes in silicon-based interlevel dielectric material layers for via holes is prevented by the use of fluorine-free etching processes. Other embodiments of the present invention include performing a two-step etching sequence comprising a first, fluorine-containing process and a second, fluorine-free process.
摘要翻译：避免或最小化了使用铜基互连金属化系统的多级半导体器件中使用的钽基粘合/阻挡层的腐蚀和降解。在本发明的实施方案中，通过使用无氟蚀刻工艺来防止由于在用于通孔的硅基层间介电材料层中蚀刻通孔而形成在下面的铜基金属特征上的有害的含氟污染物。本发明的其它实施方案包括执行包括第一含氟过程和第二无氟方法的两步蚀刻顺序。

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