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1. 发明授权

US06812158B1 Modular growth of multiple gate oxides 有权
标题翻译：多栅极氧化物的模块生长
公开(公告)号：US06812158B1
公开(公告)日：2004-11-02
申请号：US10335177
申请日：2002-12-31
申请人： Wen-Chin Yeh , Venkatesh Gopinath , Arvind Kamath
发明人： Wen-Chin Yeh , Venkatesh Gopinath , Arvind Kamath
IPC分类号： H01L2131
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31658 , H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： Growth of multiple gate oxides. By implanting different sites of a wafer with different doses of an oxide growth retardant, the entire wafer can grow oxides of different thicknesses even after being exposed to the same oxidation environment. The process is modular insofar as the implantation of one site has no effect on rate of growth of other sites.
摘要翻译：多栅极氧化物的生长。通过用不同剂量的氧化物生长阻滞剂植入晶片的不同位置，即使在暴露于相同的氧化环境之后，整个晶片也可以生长不同厚度的氧化物。该过程是模块化的，因为一个位点的植入对其他位点的生长速率没有影响。

2. 发明授权

US06989331B2 Hard mask removal 有权
标题翻译：硬面膜去除
公开(公告)号：US06989331B2
公开(公告)日：2006-01-24
申请号：US10615558
申请日：2003-07-08
申请人： Venkatesh Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee , Brian A. Baylis
发明人： Venkatesh Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee , Brian A. Baylis
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.
摘要翻译：从形成在下层上的图案化层去除硬掩模层的方法，其中使用蚀刻剂去除硬掩模层，当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层以去除硬掩模层，而不会有害地蚀刻下面的层。修改硬掩模层，使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。图案化硬掩模层。蚀刻图案层以暴露下层的部分。硬掩模层和下层的暴露部分用蚀刻剂蚀刻，其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层，这是因为硬的掩模层。

3. 发明授权

US07026217B1 Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate 失效
标题翻译：在氮化衬底的湿氧化下在半导体衬底上形成反熔丝的方法
公开(公告)号：US07026217B1
公开(公告)日：2006-04-11
申请号：US10697446
申请日：2003-10-29
申请人： Arvind Kamath , Venkatesh P. Gopinath , Wen-Chin Yeh , David Pachura
发明人： Arvind Kamath , Venkatesh P. Gopinath , Wen-Chin Yeh , David Pachura
IPC分类号： H01L21/336
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/28211 , H01L21/2822 , H01L21/28238 , H01L21/76224 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method of producing an antifuse includes introducing nitrogen by ion implantation means into the substrate. An oxide dielectric layer is then formed on the nitrided substrate in a wet oxidation ambient. The conditions of the ion implantation and the oxidation are controlled to generate a dielectric with uniform thickness and a low breakdown voltage when subjected to a high electric field.
摘要翻译：制造反熔丝的方法包括通过离子注入装置将氮引入衬底。然后在湿氧化环境中在氮化衬底上形成氧化物介电层。控制离子注入和氧化的条件以产生具有均匀厚度的电介质和当受到高电场时的低击穿电压。

4. 发明授权

US07413996B2 High k gate insulator removal 有权
标题翻译：高k栅绝缘子去除
公开(公告)号：US07413996B2
公开(公告)日：2008-08-19
申请号：US10413051
申请日：2003-04-14
申请人： Arvind Kamath , Wai Lo , Venkatesh Gopinath
发明人： Arvind Kamath , Wai Lo , Venkatesh Gopinath
IPC分类号： H01L21/00
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/31122 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an ion implanted species that causes lattice damage to the exposed portions of the high k layer. The lattice damaged exposed portions of the high k layer are etched to leave the high k gate insulation layer.
摘要翻译：在基板上的集成电路中形成高k栅极绝缘层的方法。将高k层沉积在衬底上，并用掩模图案以限定高k栅极绝缘层和高k层的暴露部分。高k层的暴露部分经受离子注入物质，其导致对高k层的暴露部分的晶格损伤。蚀刻高K层的晶格损坏的暴露部分以留下高k栅极绝缘层。

5. 发明申请

US20050006347A1 Hard mask removal 有权
标题翻译：硬面膜去除
公开(公告)号：US20050006347A1
公开(公告)日：2005-01-13
申请号：US10615558
申请日：2003-07-08
申请人： Venkatesh Gopinath , Arvind Kamath , Mohammad Mirabedini , Ming-Yi Lee , Brian Baylis
发明人： Venkatesh Gopinath , Arvind Kamath , Mohammad Mirabedini , Ming-Yi Lee , Brian Baylis
IPC分类号： H01L21/311 , C23F1/00
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.
摘要翻译：从形成在下层上的图案化层去除硬掩模层的方法，其中使用蚀刻剂去除硬掩模层，当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层以去除硬掩模层，而不会有害地蚀刻下面的层。修改硬掩模层，使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。图案化硬掩模层。蚀刻图案层以暴露下层的部分。硬掩模层和下层的暴露部分用蚀刻剂蚀刻，其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层，这是因为硬的掩模层。

6. 发明授权

US06544829B1 Polysilicon gate salicidation 有权
标题翻译：多晶硅栅盐化
公开(公告)号：US06544829B1
公开(公告)日：2003-04-08
申请号：US10251016
申请日：2002-09-20
申请人： Venkatesh Gopinath , Mohammad Mirabedini , Charles E. May , Arvind Kamath
发明人： Venkatesh Gopinath , Mohammad Mirabedini , Charles E. May , Arvind Kamath
IPC分类号： H01L218238
CPC分类号： H01L21/823835 , H01L21/823814 , H01L21/823878
摘要： A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region. The exposed second portions of the unpatterned polysilicon layer are removed to define polysilicon gate electrode precursors under the gate electrode masks. The gate electrode masks are removed from the polysilicon gate electrode precursors, and a metal layer is deposited over the polysilicon gate electrode precursors and the source drain regions. The integrated circuit substrate is annealed to substantially completely consume the polysilicon gate electrode precursors and form silicide gate electrodes from the polysilicon gate electrode precursors and the overlying metal layer, by which silicide contacts in the source drain regions are also formed.
摘要翻译：一种在CMOS工艺流程中制造基本上完全硅化的多晶硅栅电极的方法。在集成电路基板上形成硬掩模材料，其中集成电路基板包括覆盖在栅极氧化物层上的未图案化的多晶硅层和设置在隔离结构之间的阱区域。去除硬掩模材料的部分以限定覆盖未图案化多晶硅层和栅极氧化物层的第一部分的栅电极掩模，留下未图案化的多晶硅层和栅极氧化物层的暴露的第二部分。集成电路基板暴露于穿过栅极氧化物层的第二部分但不穿过限定阱区中的源极漏极区域的栅极电极掩模之下的栅极氧化物层的第一部分的掺杂剂。去除未图案化的多晶硅层的暴露的第二部分以在栅极电极掩模下限定多晶硅栅电极前体。栅极电极掩模从多晶硅栅电极前驱体去除，并且金属层沉积在多晶硅栅极电极前体和源极漏极区上。将集成电路基板退火以基本上完全消耗多晶硅栅极电极前体，并从多晶硅栅极电极前体和上覆金属层形成硅化物栅极电极，由此源极漏极区域中的硅化物接触也形成。

7. 发明授权

US08796774B2 Printed non-volatile memory 有权
标题翻译：打印的非易失性存储器
公开(公告)号：US08796774B2
公开(公告)日：2014-08-05
申请号：US13585673
申请日：2012-08-14
申请人： Arvind Kamath , Patrick Smith , James Montague Cleeves
发明人： Arvind Kamath , Patrick Smith , James Montague Cleeves
IPC分类号： H01L29/66 , H01L29/788
CPC分类号： H01L21/28518 , H01L21/288 , H01L21/76801 , H01L21/76895 , H01L27/115 , H01L27/11558 , H01L27/1292 , H01L29/66757 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.
摘要翻译：公开了一种非易失性存储单元，其具有位于相同水平位置并且间隔开预定距离的第一和第二半岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。在一个有利的实施例中，可以使用“全印刷”工艺技术来制造非易失性存储单元。

8. 发明申请

US20140094004A1 Printed Dopant Layers 有权
标题翻译：印刷掺杂层
公开(公告)号：US20140094004A1
公开(公告)日：2014-04-03
申请号：US13633816
申请日：2012-10-02
申请人： Arvind Kamath , James Montague Cleeves , Joerg Rockenberger , Patrick Smith , Fabio Zürcher
发明人： Arvind Kamath , James Montague Cleeves , Joerg Rockenberger , Patrick Smith , Fabio Zürcher
IPC分类号： H01L21/336
CPC分类号： H01L27/1292 , H01L29/66757
摘要： A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
摘要翻译：一种用于制造诸如MOS晶体管的电子器件的方法，包括以下步骤：在电功能衬底上形成多个半导体岛，在第一半导体岛子集上或第二子体上印刷第一介电层，在半导体岛的第二子集上或之上，以及退火。第一介电层包含第一掺杂剂，并且（任选的）第二介电层包含不同于第一掺杂剂的第二掺杂剂。电介质层，半导体岛和衬底被充分退火以将第一掺杂剂扩散到半导体岛的第一子集中，并且当存在时将第二掺杂剂扩散到半导体岛的第二子集中。

9. 发明授权

US08426905B2 Profile engineered, electrically active thin film devices 有权
标题翻译：型材设计，电活性薄膜器件
公开(公告)号：US08426905B2
公开(公告)日：2013-04-23
申请号：US12243880
申请日：2008-10-01
申请人： Arvind Kamath , Erik Scher , Patrick Smith , Aditi Chandra , Steven Molesa
发明人： Arvind Kamath , Erik Scher , Patrick Smith , Aditi Chandra , Steven Molesa
IPC分类号： H01L29/788
CPC分类号： H01L21/36 , C23C18/08 , C23C18/122 , C23C18/1245 , C23C18/1295 , H01L21/02532 , H01L21/02601 , H01L21/02628 , H01L21/28273 , H01L21/28518 , H01L21/288 , H01L21/76871 , H01L21/76895 , H01L27/1285 , H01L27/1292 , H01L28/40 , H01L29/0657 , H01L29/66143 , H01L29/6675 , H01L29/7881 , H01L29/872 , H05K1/16 , H05K1/162 , H05K3/125 , H05K2201/098
摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.
摘要翻译：本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

10. 发明授权

US08227320B2 High reliability surveillance and/or identification tag/devices and methods of making and using the same 有权
公开(公告)号：US08227320B2
公开(公告)日：2012-07-24
申请号：US12249735
申请日：2008-10-10
申请人： Vivek Subramanian , Patrick Smith , Vikram Pavate , Arvind Kamath , Criswell Choi , Aditi Chandra , James Montague Cleeves
发明人： Vivek Subramanian , Patrick Smith , Vikram Pavate , Arvind Kamath , Criswell Choi , Aditi Chandra , James Montague Cleeves
IPC分类号： H01L21/20
CPC分类号： G08B13/2431 , G06K19/067 , G06K19/07749 , G08B13/242 , G08B13/2437
摘要： The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.

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