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1. 发明授权

US07413996B2 High k gate insulator removal 有权
标题翻译：高k栅绝缘子去除
公开(公告)号：US07413996B2
公开(公告)日：2008-08-19
申请号：US10413051
申请日：2003-04-14
申请人： Arvind Kamath , Wai Lo , Venkatesh Gopinath
发明人： Arvind Kamath , Wai Lo , Venkatesh Gopinath
IPC分类号： H01L21/00
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/31122 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an ion implanted species that causes lattice damage to the exposed portions of the high k layer. The lattice damaged exposed portions of the high k layer are etched to leave the high k gate insulation layer.
摘要翻译：在基板上的集成电路中形成高k栅极绝缘层的方法。将高k层沉积在衬底上，并用掩模图案以限定高k栅极绝缘层和高k层的暴露部分。高k层的暴露部分经受离子注入物质，其导致对高k层的暴露部分的晶格损伤。蚀刻高K层的晶格损坏的暴露部分以留下高k栅极绝缘层。

2. 发明授权

US09274410B2 Method and system for automated generation of masks for spacer formation from a desired final wafer pattern 有权
标题翻译：用于从期望的最终晶片图案自动生成用于间隔物形成的掩模的方法和系统
公开(公告)号：US09274410B2
公开(公告)日：2016-03-01
申请号：US12701391
申请日：2010-02-05
申请人： Wai Lo , Todd Lukanc , Christie Marrian
发明人： Wai Lo , Todd Lukanc , Christie Marrian
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/14 , G03F1/70
摘要： Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.
摘要翻译：公开了用于产生用于间隔物形成的掩模的方法和系统。作为所公开的方法的一部分，访问预定义的最终晶片图案，识别与预定的最终晶片图案中的特征相关的区域，并且基于用于在晶片上形成间隔物的所识别的区域形成模板掩模。随后，形成用于去除间隔物的部分以形成对应于预定的最终晶片图案的晶片图案的掩模。

3. 发明授权

US07829936B2 Split charge storage node inner spacer process 有权
标题翻译：分离电荷存储节点内隔离过程
公开(公告)号：US07829936B2
公开(公告)日：2010-11-09
申请号：US11873822
申请日：2007-10-17
申请人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R. K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
发明人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R. K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
IPC分类号： H01L21/331
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42344
摘要： Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
摘要翻译：提供了在半导体衬底上形成包含两个分开的次光刻电荷存储节点的存储单元的方法。这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。通过去除第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。此外，通过去除电荷存储层的暴露部分，同时保留由两个分割子光刻第一多晶硅栅极保护的电荷存储层的部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个拆分次光刻电荷存储节点。

4. 发明授权

US07807580B2 Triple poly-si replacement scheme for memory devices 有权
标题翻译：存储器件的三重多晶硅替代方案
公开(公告)号：US07807580B2
公开(公告)日：2010-10-05
申请号：US11742003
申请日：2007-04-30
申请人： Chungho Lee , Huaqiang Wu , Wai Lo , Hiroyuki Kinoshita
发明人： Chungho Lee , Huaqiang Wu , Wai Lo , Hiroyuki Kinoshita
IPC分类号： H01L21/302
CPC分类号： H01L27/11573 , H01L21/28282
摘要： A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions.
摘要翻译：提供了替换存储器件的存储元件周围的顶部氧化物的方法。该方法可以包括在核心区域中去除核心的第一多核和第一顶部氧化物，而不去除半导体衬底上的外围区域中的周边第一多晶硅; 在所述芯区域中的存储元件周围和所述周边区域的所述外围第一聚四氟乙烯上形成第二顶部氧化物; 在所述芯和外围区域中在所述半导体衬底上形成第二聚合物; 去除所述周边区域中的所述第二聚合物和第二顶部氧化物; 以及在所述芯和外围区域中在所述半导体衬底上形成第三聚合物。

5. 发明申请

US20080150090A1 DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL 审中-公开
标题翻译：使用Si1-xGex作为材料的具有控制门型材和长度的金属浇注过程
公开(公告)号：US20080150090A1
公开(公告)日：2008-06-26
申请号：US12021728
申请日：2008-01-29
申请人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
发明人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
IPC分类号： H01L29/40
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
摘要翻译：一种在晶片中形成金属栅极的方法。多晶硅1-x x Ge x S和多晶硅用于形成锥形槽。栅极氧化物，多晶硅1-x x Ge x，并且多晶硅沉积在晶片上。形成抗蚀剂图案。去除多晶硅的一部分，多晶硅1-x N x N x N和栅极氧化物以提供锥形轮廓。去除抗蚀剂; 沉积电介质衬垫，然后去除电介质衬垫的至少一部分，从而暴露多晶硅并使电介质衬垫与多晶硅接触，多晶硅1-x Ge x 和/或栅极氧化物。沉积电介质，一部分被去除，从而暴露多晶硅。从电介质衬垫的内部去除多晶硅，多晶硅1 x x Ge x x和栅极氧化物，从而留下锥形栅极沟槽。然后将金属沉积在凹槽中。

6. 发明授权

US07259462B1 Interconnect dielectric tuning 有权
标题翻译：互连电介质调谐
公开(公告)号：US07259462B1
公开(公告)日：2007-08-21
申请号：US11419548
申请日：2006-05-22
申请人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.
摘要翻译：对形成集成电路的方法的改进。形成蚀刻停止层以覆盖集成电路的前端处理层。形成支撑结构，其被布置为支撑集成电路的各个级别上的导电互连。基本上去除了在制造互连期间形成的蚀刻停止层上方的所有非导电层。

7. 发明申请

US20060166745A1 Handheld electronic game with recharging function 审中-公开
标题翻译：手持电子游戏充电功能
公开(公告)号：US20060166745A1
公开(公告)日：2006-07-27
申请号：US11042733
申请日：2005-01-24
申请人： Wai Lo
发明人： Wai Lo
IPC分类号： A63F9/24
CPC分类号： A63F13/92 , A63F13/08 , A63F2300/204
摘要： A handheld electronic game comprises a rotational body, an processor, a storage cell for powering the processor, a display screen for displaying images processed by the processor, and a number of keys for providing game-control input to the processor. A generator is electrically connected to the storage cell for applying voltage to and recharging the storage cell. There is also a flywheel rotatably with respect to the body, which is connected to the generator and provides a mass moment of inertia enabling rotation of the body relative thereto during dynamic rotational movement of the body.
摘要翻译：手持电子游戏包括旋转体，处理器，用于为处理器供电的存储单元，用于显示由处理器处理的图像的显示屏幕以及用于向处理器提供游戏控制输入的多个键。发电机电连接到存储单元，用于向存储单元施加电压和再充电。还有一个相对于主体可旋转的飞轮，其连接到发电机并且提供质量惯性矩，使得主体在主体的动态旋转运动期间相对于其旋转。

8. 发明授权

US06864141B1 Method of incorporating nitrogen into metal silicate based dielectrics by energized nitrogen ion beams 有权
标题翻译：通过激励氮离子束将氮掺入金属硅酸盐基电介质的方法
公开(公告)号：US06864141B1
公开(公告)日：2005-03-08
申请号：US10453118
申请日：2003-06-03
申请人： Wai Lo , James P. Kimball , Verne C. Hornback
发明人： Wai Lo , James P. Kimball , Verne C. Hornback
IPC分类号： H01L21/28 , H01L21/3115 , H01L21/314 , H01L21/8238 , H01L29/51 , H01L21/283 , H01L21/31
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L21/823857 , H01L29/518
摘要： A method of making a thin gate dielectric includes providing a metal silicate on a silicon substrate. Nitrogen is implanted into the metal silicate.
摘要翻译：制造薄栅极电介质的方法包括在硅衬底上提供金属硅酸盐。将氮气注入到金属硅酸盐中。

9. 发明授权

US06849512B1 Thin gate dielectric for a CMOS transistor and method of fabrication thereof 失效
标题翻译： CMOS晶体管的薄栅极电介质及其制造方法
公开(公告)号：US06849512B1
公开(公告)日：2005-02-01
申请号：US10283630
申请日：2002-10-30
申请人： Wai Lo , James P. Kimball , Verne C. Hornback
发明人： Wai Lo , James P. Kimball , Verne C. Hornback
IPC分类号： H01L21/265 , H01L21/28 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28211 , H01L21/26506 , H01L21/2822 , H01L21/28238 , H01L29/518
摘要： A method of making a thin gate dielectric includes implanting a barrier substance into a region of a silicon substrate. A capacitance-increasing material is implanted into the silicon substrate. An outside layer of the silicon substrate is oxidized to form a first silicon oxide layer. The silicon substrate is oxidized between the first silicon oxide layer and the region.
摘要翻译：制造薄栅极电介质的方法包括将阻挡物质注入到硅衬底的区域中。将电容增加材料注入到硅衬底中。硅衬底的外层被氧化以形成第一氧化硅层。硅衬底在第一氧化硅层和区域之间被氧化。

10. 发明授权

US06830943B1 Thin film CMOS calibration standard having protective cover layer 失效
标题翻译：具有保护层的薄膜CMOS校准标准
公开(公告)号：US06830943B1
公开(公告)日：2004-12-14
申请号：US10702165
申请日：2003-11-04
申请人： Wai Lo , David Chan
发明人： Wai Lo , David Chan
IPC分类号： H01L2166
CPC分类号： H01L22/34 , G01B11/0616
摘要： Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and protective layer are each formed to precise tolerances. The invention also includes methods for forming a calibration standard for semiconductor metrology tools.
摘要翻译：本发明的实施例包括用于半导体计量工具的校准标准。该标准包括具有在其上形成有校准层的表面的基板。在底层校准层上形成保护层。校准层和保护层各自形成为精确的公差。本发明还包括形成用于半导体计量工具的校准标准的方法。

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