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    • 1. 发明申请
    • Hard mask removal
    • 硬面膜去除
    • US20050006347A1
    • 2005-01-13
    • US10615558
    • 2003-07-08
    • Venkatesh GopinathArvind KamathMohammad MirabediniMing-Yi LeeBrian Baylis
    • Venkatesh GopinathArvind KamathMohammad MirabediniMing-Yi LeeBrian Baylis
    • H01L21/311C23F1/00
    • H01L21/31144H01L21/31116
    • A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.
    • 从形成在下层上的图案化层去除硬掩模层的方法,其中使用蚀刻剂去除硬掩模层,当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层 以去除硬掩模层,而不会有害地蚀刻下面的层。 修改硬掩模层,使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。 图案化硬掩模层。 蚀刻图案层以暴露下层的部分。 硬掩模层和下层的暴露部分用蚀刻剂蚀刻,其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层,这是因为硬的 掩模层。
    • 4. 发明授权
    • Polysilicon gate salicidation
    • 多晶硅栅盐化
    • US06544829B1
    • 2003-04-08
    • US10251016
    • 2002-09-20
    • Venkatesh GopinathMohammad MirabediniCharles E. MayArvind Kamath
    • Venkatesh GopinathMohammad MirabediniCharles E. MayArvind Kamath
    • H01L218238
    • H01L21/823835H01L21/823814H01L21/823878
    • A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region. The exposed second portions of the unpatterned polysilicon layer are removed to define polysilicon gate electrode precursors under the gate electrode masks. The gate electrode masks are removed from the polysilicon gate electrode precursors, and a metal layer is deposited over the polysilicon gate electrode precursors and the source drain regions. The integrated circuit substrate is annealed to substantially completely consume the polysilicon gate electrode precursors and form silicide gate electrodes from the polysilicon gate electrode precursors and the overlying metal layer, by which silicide contacts in the source drain regions are also formed.
    • 一种在CMOS工艺流程中制造基本上完全硅化的多晶硅栅电极的方法。 在集成电路基板上形成硬掩模材料,其中集成电路基板包括覆盖在栅极氧化物层上的未图案化的多晶硅层和设置在隔离结构之间的阱区域。 去除硬掩模材料的部分以限定覆盖未图案化多晶硅层和栅极氧化物层的第一部分的栅电极掩模,留下未图案化的多晶硅层和栅极氧化物层的暴露的第二部分。 集成电路基板暴露于穿过栅极氧化物层的第二部分但不穿过限定阱区中的源极漏极区域的栅极电极掩模之下的栅极氧化物层的第一部分的掺杂剂。 去除未图案化的多晶硅层的暴露的第二部分以在栅极电极掩模下限定多晶硅栅电极前体。 栅极电极掩模从多晶硅栅电极前驱体去除,并且金属层沉积在多晶硅栅极电极前体和源极漏极区上。 将集成电路基板退火以基本上完​​全消耗多晶硅栅极电极前体,并从多晶硅栅极电极前体和上覆金属层形成硅化物栅极电极,由此源极漏极区域中的硅化物接触也形成。