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    • 1. 发明授权
    • Memory array
    • 内存阵列
    • US08693243B2
    • 2014-04-08
    • US13253855
    • 2011-10-05
    • Jing GuBo ZhangWeiran KongJian Hu
    • Jing GuBo ZhangWeiran KongJian Hu
    • G11C11/34
    • G11C16/26G11C16/0458G11C16/10H01L21/28273H01L29/42332H01L29/7887
    • A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.
    • 在半导体技术领域中使用的存储器阵列包括多个存储单元,位线,垂直于位线的字线和第一/第二控制线。 存储器阵列使用分裂门存储器单元,其中存储器单元的两个存储器位单元共享一个字线,从而可以通过向字线施加不同的电压来实现存储器单元的读取,编程和擦除,两个控制栅极 和源极/漏极区域; 字线共享结构使得分闸器闪存能够有效地减小芯片面积并避免过度擦除问题,同时保持芯片的电隔离性能不变,而不会增加工艺的复杂性。
    • 2. 发明申请
    • Memory Array
    • 内存阵列
    • US20120206969A1
    • 2012-08-16
    • US13253855
    • 2011-10-05
    • Jing GuBo ZhangWeiran KongJian Hu
    • Jing GuBo ZhangWeiran KongJian Hu
    • G11C16/04H01L29/788
    • G11C16/26G11C16/0458G11C16/10H01L21/28273H01L29/42332H01L29/7887
    • A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.
    • 在半导体技术领域中使用的存储器阵列包括多个存储单元,位线,垂直于位线的字线和第一/第二控制线。 存储器阵列使用分裂门存储器单元,其中存储器单元的两个存储器位单元共享一个字线,从而可以通过向字线施加不同的电压来实现存储器单元的读取,编程和擦除,两个控制栅极 和源极/漏极区域; 字线共享结构使得分闸器闪存能够有效地减小芯片面积并避免过度擦除问题,同时保持芯片的电隔离性能不变,而不会增加工艺的复杂性。