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1. 发明授权

US5386384A Parallel CCD memory chip and method of matching therewith 失效
标题翻译：并行CCD存储芯片及其匹配方法
公开(公告)号：US5386384A
公开(公告)日：1995-01-31
申请号：US28124
申请日：1993-03-09
申请人： Volnei A. Pedroni , Amnon Yariv , Aharon J. Agranat
发明人： Volnei A. Pedroni , Amnon Yariv , Aharon J. Agranat
IPC分类号： G11C15/00 , G11C19/28 , H03K23/46
CPC分类号： G11C15/00 , G11C19/282 , G11C19/287
摘要： A fully parallel CCD memory chip of N address lines which detects in just one clock cycle, a perfect match between an input pattern and any of a plurality of stored patterns and also detects in less than (N+1)-comparison cycles and still just one XOR operation, the best matching in case a perfect one does not exist. The chip disclosed herein has a fully parallel architecture in which an input word is compared to all stored words at one time. A preferred embodiment of the invention uses a four phase CCD, wherein each stored word occupies one row of the CCD and each such bit of each such word occupies two cells. Where perfect matches exist, only one comparison clock cycle is needed to compare the input word with all stored words and where there is no perfect match, the best match will be detected on a subsequent comparison pulse. Charge packets represent binary words generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines. The sensing is done directly on the cells in a non-destructive sensing process in parallel, rather than at the end of each row.
摘要翻译：一个完全并行的N个地址线的CCD存储芯片，只需一个时钟周期即可检测输入模式与多种存储模式中的任一种之间的完美匹配，并且还可以在少于（N + 1）个比较周期内进行检测一个XOR操作，最好的匹配，一个完美的不存在的情况。本文公开的芯片具有完全并行的架构，其中输入字被一次与所有存储的字进行比较。本发明的优选实施例使用四相CCD，其中每个存储的字占据CCD的一行，并且每个这样的字的每个这样的位占据两个单元。在存在完美匹配的情况下，仅需要一个比较时钟周期来比较输入字与所有存储字，并且在没有完美匹配的情况下，将在随后的比较脉冲中检测最佳匹配。充电分组表示由通过数据输入线施加到芯片的外部脉冲产生的二进制字，然后与施加到地址线的数据进行比较。在非破坏性感测过程中，并行地而不是在每一行的末端，在单元上直接进行感测。

2. 发明授权

US5724269A Single clock cycle two-dimensional median filter 失效
标题翻译：单时钟周期二维中值滤波器
公开(公告)号：US5724269A
公开(公告)日：1998-03-03
申请号：US514626
申请日：1995-08-14
申请人： Volnei A. Pedroni , Amnon Yariv
发明人： Volnei A. Pedroni , Amnon Yariv
IPC分类号： H03H17/02 , G06F17/00
CPC分类号： H03H17/0202
摘要： A median circuit operates over a single-clock-cycle to determine the median of the group. Each value is compared with a plurality of other values. One of those other values become the eventual median. The possible median which is closest to all of the elements being compared is taken as the overall closest value and established as the median. Most specifically, this is done by applying the higher voltage of the pair to one end of a capacitor at the same time as a precharge. After the precharge is complete, the lower voltage of the pair is applied to the capacitor. The capacitor acts as a charge pump, lowering its other end by an amount proportional to the distance between the higher voltage of the pair and the lower voltage of the pair. A plurality of the capacitors are connected together, so that the output from the group of cells represents the average capacitors among all elements. The highest group represents the eventual median.
摘要翻译：中值电路在单个时钟周期内工作，以确定组的中位数。将每个值与多个其他值进行比较。其中一个值成为最终的中位数。最接近所有要比较的元素的可能中位数作为总体最接近的值，并被确定为中位数。最具体地说，这是通过在预充电的同时将该对的较高电压施加到电容器的一端来完成的。预充电完成后，该对的较低电压被施加到电容器。电容器充当电荷泵，将其另一端的数量与成对的较高电压和对电压的较低电压之间的距离成正比。多个电容器连接在一起，使得来自该单元组的输出表示所有元件之间的平均电容器。最高组代表最终中位数。

3. 发明授权

US5270559A Method and apparatus for making highly accurate potential well adjustments in CCD's 失效
标题翻译：在CCD中进行高精度势阱调整的方法和装置
公开(公告)号：US5270559A
公开(公告)日：1993-12-14
申请号：US967383
申请日：1992-10-29
申请人： Amnon Yariv , Charles F. Neugebauer , Aharon J. Agranat
发明人： Amnon Yariv , Charles F. Neugebauer , Aharon J. Agranat
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/42396
摘要： An adjustable CCD gate structure utilizing ultra-violet light activated floating gates, wherein a floating polysilicon gate is used between a CCD electrode and the underlying substrate to provide a fixed voltage bias to the CCD gate during the manufacturing process thereof The floating gate is programmed with a desired voltage bias during the application of ultra-violet light and is thereafter fixed at that adjusted level, upon the removal of the ultra-violet light. Thus, the method of the present invention comprises the steps of providing a CCD gate structure in which there is such a floating polysilicon gate between the CCD electrode and the underlying substrate; applying an ultra-violet light activation to the floating polysilicon gate; applying a voltage to the conventional CCD electrode which is resistively coupled to the floating electrode for adjusting the bias on the floating electrode to a desired level; and then removing the ultra-violet light to fix the voltage bias at the floating polysilicon gate at a permanant level.
摘要翻译：利用紫外光激活浮栅的可调CCD门结构，其中在CCD电极和底层衬底之间使用浮动多晶硅栅极，以在其制造过程期间向CCD栅极提供固定的电压偏置。浮栅用在施加紫外光期间的期望的电压偏压，然后在去除紫外线时固定在该调节水平。因此，本发明的方法包括以下步骤：提供CCD栅极结构，其中在CCD电极和下面的衬底之间存在这样的浮置多晶硅栅极; 将紫外光激活施加到浮动多晶硅栅极; 向传统的CCD电极施加电压，该CCD电极电阻耦合到浮动电极，用于将浮动电极上的偏压调节至所需的电平; 然后去除紫外光以将浮动多晶硅栅极处的电压偏置固定在永久水平。

4. 发明授权

US5353382A Programmable synapse for neural network applications 失效
标题翻译：神经网络应用的可编程突触
公开(公告)号：US5353382A
公开(公告)日：1994-10-04
申请号：US597390
申请日：1990-10-15
申请人： Amnon Yariv , Charles F. Neugebauer , Aharon J. Agranat
发明人： Amnon Yariv , Charles F. Neugebauer , Aharon J. Agranat
IPC分类号： G06N3/063 , H03K19/21
CPC分类号： G06N3/063
摘要： A synapse for neural network applications providing four quadrant feed-forward and feed-back modes in addition to an outer-product learning capability allowing learning in-situ. The invention, in its preferred embodiment, utilizes a novel two-transistor implementation which permits each synapse to be built in an integrated circuit chip surface area of only 20 by 20 micrometers. One of the two transistors at each synapse of the present invention comprises a floating gate structure composed of a floating gate electrode and a control electrode which permits learning upon application of incident ultraviolet light. During ultraviolet light application, a floating gate electrode voltage may be altered to modify the weight of each synapse in accordance with preselected criteria, based upon the input and output weight change vector elements corresponding to that particular matrix element. The second transistor corresponding to each synapse of the present invention provides a novel method for applying a voltage to the control electrode of the aforementioned floating gate structure of the first transistor. The voltage applied to the control electrode and thus the proportionate change in the floating gate electrode of the first transistor may be made proportional to the product of the corresponding input weight change vector element and the corresponding output weight change vector element, by using slope controllable ramp generators and phase controllable pulse generators, only one set of which must be provided for the entire matrix of synapses herein disclosed.
摘要翻译：提供四象限前馈和反馈模式的神经网络应用程序的突触，以及允许原位学习的外部产品学习能力。在其优选实施例中，本发明利用了一种新颖的双晶体管实现，其允许每个突触内置在只有20×20微米的集成电路芯片表面积中。在本发明的每个突触处的两个晶体管中的一个包括由浮置栅极电极和控制电极构成的浮动栅极结构，其允许在施加入射的紫外光时学习。在紫外线照射期间，可以根据与特定矩阵元素对应的输入和输出权重变化向量元素，根据预先选择的标准改变浮栅电极电压以改变每个突触的重量。对应于本发明的每个突触的第二晶体管提供了一种向第一晶体管的上述浮置栅极结构的控制电极施加电压的新方法。施加到控制电极的电压以及因此第一晶体管的浮置栅电极的比例变化可以通过使用斜率可控斜坡与相应的输入权重变化向量元素和相应的输出权重变化向量元素的乘积成比例发生器和相位可控脉冲发生器，必须为本文公开的突触整个基体提供其中一组。

5. 发明授权

US5258934A Charge domain bit serial vector-matrix multiplier and method thereof 失效
标题翻译：电荷域位串行矢量矩阵乘法器及其方法
公开(公告)号：US5258934A
公开(公告)日：1993-11-02
申请号：US522772
申请日：1990-05-14
申请人： Aharon J. Agranat , Charles F. Neugebauer , Amnon Yariv
发明人： Aharon J. Agranat , Charles F. Neugebauer , Amnon Yariv
IPC分类号： G06E1/04 , G06N3/067 , G06G7/16 , G06J7/12
CPC分类号： G06E1/045 , G06N3/0675
摘要： A charge domain bit serial vector matrix multiplier for real time signal processing of mixed digital/analog signals for implementing opto-electronic neural networks and other signal processing functions. A combination of CCD and DCSD arrays permits vector/matrix multiplication with better than 10.sup.11 multiply accumulates per second on a one square centimeter chip. The CCD array portion of the invention is used to load and move charge packets into the DCSD array for processing therein. The CCD array is also used to empty the matrix of unwanted charge. The DCSD array is designed to store a plurality of charge packets representing the respective matrix values such as the synaptic interaction matrix of a neural network. The vector multiplicand may be applied in bit serial format. The row or sensor lines of the DCSD array are used to accumulate the results of the multiply operation. Each such row output line is provided with a divide-by-two/accumulate CCD circuit which automatically compensates for the increasing value of the input vector element's bits from least significant bit to most significant bit. In a similar fashion each row output line can be provided with a multiply-by-two/accumulate CCD circuit which automatically accounts for the decreasing value of the input vector element's bits from most significant bit to least significant bit. The accumulated charge packet output of the array may be preferably converted to a digital signal compatible with the input vector configuration by utilizing a plurality of analog-to-digital converters.
摘要翻译：一种电荷域位串行矢量矩阵乘法器，用于实现光电神经网络和其他信号处理功能的混合数字/模拟信号的实时信号处理。 CCD和DCSD阵列的组合允许在一平方厘米芯片上以每秒1011次乘积累加的向量/矩阵乘法。本发明的CCD阵列部分用于加载和移动电荷包到DCSD阵列中以在其中进行处理。 CCD阵列也用于清空不需要的电荷的矩阵。 DCSD阵列被设计为存储表示各个矩阵值的多个电荷分组，例如神经网络的突触相互作用矩阵。向量被乘数可以位串行格式应用。 DCSD阵列的行或传感器线用于累加乘法运算的结果。每个这样的行输出线被提供有二分频/累积CCD电路，其自动补偿从最低有效位到最高有效位的输入向量元素的比特的增加值。以类似的方式，每行输出线可以被提供有乘以二/累积的CCD电路，其自动地将输入向量元素的位的值从最高有效位到最低有效位解算。通过利用多个模数转换器，阵列的累积电荷分组输出可以优选地被转换成与输入矢量配置兼容的数字信号。

6. 发明授权

US5008833A Parallel optoelectronic neural network processors 失效
标题翻译：平行光电神经网络处理器
公开(公告)号：US5008833A
公开(公告)日：1991-04-16
申请号：US495781
申请日：1990-03-19
申请人： Aharon J. Agranat , Charles F. Neugebauer , Amnon Yariv
发明人： Aharon J. Agranat , Charles F. Neugebauer , Amnon Yariv
IPC分类号： G06N3/063 , G06N3/067
CPC分类号： G06N3/0675 , G06N3/063
摘要： Several embodiments of neural processors implemented on a VLSI circuit chip are disclosed, all of which are capable of entering a matrix T into an array of photosensitive devices which may be charge coupled or charge injection devices (CCD or CID). Using CCD's to receive and store the synapses of the matrix T from a spatial light modulator, or other optical means of projecting an array of pixels, semiparallel synchronous operation is achieved. Using CID's, full parallel synchronous operation is achieved. And using phototransistors to receive the array of pixels, full parallel and asynchronous operation is achieved. In the latter case, the source of the pixel matrix must provide the memory necessary for the matrix T. In the other cases, the source of the pixel matrix may be turned off after the matrix T has been entered and stored by the CCD's or CID's.
摘要翻译：公开了在VLSI电路芯片上实现的神经处理器的几个实施例，所有这些实施例都能够将矩阵T输入到可以是电荷耦合或电荷注入装置（CCD或CID）的光敏器件的阵列中。使用CCD从空间光调制器或投影像素阵列的其他光学装置接收和存储矩阵T的突触，实现了半平行同步操作。使用CID，实现了全并行同步操作。并且使用光电晶体管接收像素阵列，实现完全并行和异步操作。在后一种情况下，像素矩阵的源必须提供矩阵T所需的存储器。在其他情况下，可以在矩阵T被输入并被CCD或CID的存储器。

7. 发明授权

US5054040A Non-destructive charge domain multiplier and process thereof 失效
标题翻译：非破坏性电荷域倍增器及其工艺
公开(公告)号：US5054040A
公开(公告)日：1991-10-01
申请号：US534250
申请日：1990-06-07
申请人： Amnon Yariv , Charles T. Neugebauer , Aharon J. Agranat
发明人： Amnon Yariv , Charles T. Neugebauer , Aharon J. Agranat
IPC分类号： G11C19/28
CPC分类号： G11C19/285
摘要： A non-destructive charge domain multiplier and process thereof wherein the unique characteristics of the charge coupled device permits sensing the size of the charge packet as it moves past an electrode and creating a new charge packet proportional to the product of the original packet and an externally applied value. The device non-destructively senses the size of the charge packet and multiplies it with another value using a multiple metering gate variation of the "Fill and Spill" technique. The present invention therefore constitutes a unique CCD configuration which creates as an output, a charge packet proportional to the product of the charge in an input packet and an externally applied value. Thus, the present invention enables the performance of non-linear operations by CCD integrated circuits.
摘要翻译：一种非破坏性电荷域倍增器及其过程，其中电荷耦合器件的独特特性允许在电荷包移动通过电极时感测电荷包的尺寸，并产生与原始包和外部产品成比例的新电荷包应用价值。该装置非破坏性地感测电荷分组的大小，并使用“填充和溢出”技术的多个计量门变化将其与另一个值相乘。因此，本发明构成了独特的CCD配置，其产生与输入分组中的电荷与外部应用值成正比的电荷分组作为输出。因此，本发明能够实现CCD集成电路的非线性操作。

8. 发明授权

US09164236B2 Methods and systems for delaying optical waves 有权
标题翻译：延迟光波的方法和系统
公开(公告)号：US09164236B2
公开(公告)日：2015-10-20
申请号：US13460638
申请日：2012-04-30
申请人： Hsi-Chun Liu , Amnon Yariv
发明人： Hsi-Chun Liu , Amnon Yariv
IPC分类号： G02B6/26 , G02B6/28 , G02B6/293 , G02B6/35
CPC分类号： G02B6/2861 , G02B6/26 , G02B6/262 , G02B6/29338 , G02B6/29343 , G02B6/29383 , G02B6/29394 , G02B6/3596 , G02B27/0012
摘要： Coupled-resonator optical waveguides (CROW) can be used to control a speed of an optical signal. In particular, the coupling distance between the resonators can be adjusted to precisely control a group delay of an optical wave. Systems and methods are described to control such coupling distance in a CROW.
摘要翻译：耦合谐振器光波导（CROW）可用于控制光信号的速度。特别地，可以调节谐振器之间的耦合距离以精确地控制光波的群延迟。描述了系统和方法来控制CROW中的这种耦合距离。

9. 发明申请

US20120262721A1 Arbitrary Optical Waveform Generation Utilizing Optical Phase-Locked Loops 有权
标题翻译：使用光锁相环的任意光波生成
公开(公告)号：US20120262721A1
公开(公告)日：2012-10-18
申请号：US13451489
申请日：2012-04-19
申请人： George Rakuljic , Naresh Satyan , Arseny Vasilyev , Amnon Yariv
发明人： George Rakuljic , Naresh Satyan , Arseny Vasilyev , Amnon Yariv
IPC分类号： G01B9/02
CPC分类号： G01D5/268 , G01D5/266 , G01S7/4911 , G02F1/3536 , G02F1/365 , G02F2001/212 , G02F2201/205 , G02F2201/58 , G02F2202/108 , G02F2203/13 , H01S5/0687
摘要： This invention relates to opto-electronic systems using semiconductor lasers driven by optical phase-locked loops that control the laser's optical phase and frequency. Feedback control provides a means for precise, wideband control of optical frequency and phase, augmented further by four wave mixing stages and digitally stitched independent optical waveforms for enhanced tunability.
摘要翻译：本发明涉及使用由控制激光器的光学相位和频率的光学锁相环驱动的半导体激光器的光电子系统。反馈控制提供了一种用于精确，宽频带控制光频率和相位的手段，进一步通过四个波混频阶段和数字缝合的独立光波形进一步增强，以增强可调性。

10. 发明申请

US20100085992A1 Arbitrary Optical Waveform Generation Utilizing Optical Phase-Locked Loops 有权
标题翻译：使用光锁相环的任意光波生成
公开(公告)号：US20100085992A1
公开(公告)日：2010-04-08
申请号：US12540643
申请日：2009-08-13
申请人： George Rakuljic , Naresh Satyan , Arseny Vasilyev , Amnon Yariv
发明人： George Rakuljic , Naresh Satyan , Arseny Vasilyev , Amnon Yariv
IPC分类号： H01S3/10
CPC分类号： G01D5/268 , G01D5/266 , G01S7/4911 , G02F1/3536 , G02F1/365 , G02F2001/212 , G02F2201/205 , G02F2201/58 , G02F2202/108 , G02F2203/13 , H01S5/0687
摘要： This invention relates to opto-electronic systems using semiconductor lasers driven by optical phase-locked loops that control the laser's optical phase and frequency. Feedback control provides a means for precise, wideband control of optical frequency and phase, augmented further by four wave mixing stages and digitally stitched independent optical waveforms for enhanced tunability.
摘要翻译：本发明涉及使用由控制激光器的光学相位和频率的光学锁相环驱动的半导体激光器的光电子系统。反馈控制提供了一种用于精确，宽频带控制光频率和相位的手段，进一步通过四个波混频阶段和数字缝合的独立光波形进一步增强，以增强可调性。

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