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1. 发明申请

US20080246646A1 Charge-domain pipelined analog-to-digital converter 有权
标题翻译：电荷域流水线模数转换器
公开(公告)号：US20080246646A1
公开(公告)日：2008-10-09
申请号：US12009615
申请日：2008-01-18
申请人： Michael P. Anthony , Jefery D. Kurtze
发明人： Michael P. Anthony , Jefery D. Kurtze
IPC分类号： H03M1/12 , H03K23/46
CPC分类号： H03M1/002 , G11C27/024 , H03M1/0682 , H03M1/44
摘要： An ADC implementation of a bucket brigade type charge transfer pipeline using Metal Oxide Semiconductor (MOS) Bucket Brigade Devices (BBDs) that can be used in Analog-to-Digital (A/D) converters and other applications. In one embodiment a control circuit provides independent control of charge storage and charge transfer timing. Other arrangements provide high-speed and high-accuracy (A/D) conversion by employing a “boosted” charge-transfer circuit. The implementation can also achieve lower power consumption and improved resolution compared to other charge-domain methods by the use of a tapered pipeline, in which the amount of charge being processed is reduced in later pipeline stages compared to earlier ones. Still other embodiments enable implementing more than one decision threshold per stage, to support multi-bit resolution per stage and RSD-type A/D conversion algorithms.
摘要翻译：使用可用于模数（A / D）转换器和其他应用的金属氧化物半导体（MOS）铲斗装置（BBD）的桶式大队型电荷转移管线的ADC实现。在一个实施例中，控制电路提供对电荷存储和电荷转移定时的独立控制。其他布置通过采用“升压”电荷转移电路提供高速和高精度（A / D）转换。与其他电荷域方法相比，通过使用锥形管道，该实施方案还可以实现更低的功耗和更高的分辨率，其中在较晚的流水线阶段中，与先前的管道相比，处理的电荷量减少。其他实施例使得能够在每个阶段实现多于一个的判定阈值，以支持每个阶段的多位分辨率和RSD型A / D转换算法。

2. 发明授权

US07315330B2 Solid-state image pickup element including a thinning method to discharge unnecessary image data 失效
标题翻译：固态图像拾取元件包括用于排出不必要的图像数据的稀疏方法
公开(公告)号：US07315330B2
公开(公告)日：2008-01-01
申请号：US11159952
申请日：2005-06-23
申请人： Masaharu Hamasaki
发明人： Masaharu Hamasaki
IPC分类号： H04N5/225 , H04N3/14 , H04N5/335 , H04N5/222 , H03K23/46 , H01L27/00
CPC分类号： H04N5/3728 , H01L27/14806 , H01L27/14843 , H04N5/3456 , H04N5/361
摘要： In a case where a thinning operation is implemented at the point when signal charges are read out from each of pixels to thin out pixel information by lines (row), the thinning may be performed only in the vertical direction, but not in the horizontal direction. In an all-pixel-read-out type CCD image pickup element, a discharge controlling section is provided in each of VH transfer stage sections transferring signal charges from vertical CCDs to a horizontal CCD, and where a thinning mode is selected, among those signal charges transferred from a plurality of the vertical CCDs, those of a given set of columns are stopped and discharged at the respective discharge controlling sections, and those of the rest of columns are transferred to the horizontal CCD, and at the same time, those of a given set of lines (rows) are stopped and discharged for all columns, thereby performing the thinning operation over the pixel information in both the vertical and horizontal directions at the VH transfer stage.
摘要翻译：在从每个像素读出信号电荷并通过行（行）来稀释像素信息的点实现间隔操作的情况下，可以仅在垂直方向上而不是在水平方向上执行间隔。在全像素读出型CCD图像拾取元件中，在VH传送级部分中设置放电控制部分，其将信号电荷从垂直CCD传输到水平CCD，并且在那些信号中选择了稀疏模式从多个垂直CCD传送的电荷，给定的一组列的电荷在各个放电控制部分被停止并放电，其余的列被转移到水平CCD，同时，针对所有列停止给定的行（行）给定的一组，从而在VH传送阶段对垂直和水平方向的像素信息进行稀疏操作。

3. 发明授权

US5386384A Parallel CCD memory chip and method of matching therewith 失效
标题翻译：并行CCD存储芯片及其匹配方法
公开(公告)号：US5386384A
公开(公告)日：1995-01-31
申请号：US28124
申请日：1993-03-09
申请人： Volnei A. Pedroni , Amnon Yariv , Aharon J. Agranat
发明人： Volnei A. Pedroni , Amnon Yariv , Aharon J. Agranat
IPC分类号： G11C15/00 , G11C19/28 , H03K23/46
CPC分类号： G11C15/00 , G11C19/282 , G11C19/287
摘要： A fully parallel CCD memory chip of N address lines which detects in just one clock cycle, a perfect match between an input pattern and any of a plurality of stored patterns and also detects in less than (N+1)-comparison cycles and still just one XOR operation, the best matching in case a perfect one does not exist. The chip disclosed herein has a fully parallel architecture in which an input word is compared to all stored words at one time. A preferred embodiment of the invention uses a four phase CCD, wherein each stored word occupies one row of the CCD and each such bit of each such word occupies two cells. Where perfect matches exist, only one comparison clock cycle is needed to compare the input word with all stored words and where there is no perfect match, the best match will be detected on a subsequent comparison pulse. Charge packets represent binary words generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines. The sensing is done directly on the cells in a non-destructive sensing process in parallel, rather than at the end of each row.
摘要翻译：一个完全并行的N个地址线的CCD存储芯片，只需一个时钟周期即可检测输入模式与多种存储模式中的任一种之间的完美匹配，并且还可以在少于（N + 1）个比较周期内进行检测一个XOR操作，最好的匹配，一个完美的不存在的情况。本文公开的芯片具有完全并行的架构，其中输入字被一次与所有存储的字进行比较。本发明的优选实施例使用四相CCD，其中每个存储的字占据CCD的一行，并且每个这样的字的每个这样的位占据两个单元。在存在完美匹配的情况下，仅需要一个比较时钟周期来比较输入字与所有存储字，并且在没有完美匹配的情况下，将在随后的比较脉冲中检测最佳匹配。充电分组表示由通过数据输入线施加到芯片的外部脉冲产生的二进制字，然后与施加到地址线的数据进行比较。在非破坏性感测过程中，并行地而不是在每一行的末端，在单元上直接进行感测。

4. 发明授权

US07643072B2 Signal processing method for image capturing apparatus, and image capturing apparatus including calculating image transfer efficiency 失效
标题翻译：用于图像捕获装置的信号处理方法和包括计算图像传送效率的图像捕获装置
公开(公告)号：US07643072B2
公开(公告)日：2010-01-05
申请号：US11488688
申请日：2006-07-19
申请人： Tetsuro Ashida , Kousuke Irie , Hitoshi Yamashita , Tooru Ueda , Kenkichi Hayashi , Takeshi Miyashita
发明人： Tetsuro Ashida , Kousuke Irie , Hitoshi Yamashita , Tooru Ueda , Kenkichi Hayashi , Takeshi Miyashita
IPC分类号： H04N5/235 , H04N9/64 , H04N3/15 , H04N5/335 , H03K23/46
CPC分类号： H04N9/045 , H04N1/6086 , H04N5/361 , H04N5/37213 , H04N9/735 , H04N17/002
摘要： The present invention provides an image capturing apparatus which enables a desired image quality to be maintained regardless of transfer efficiency of a CCD image capturing element. R, G and B signals (CCD-RAW data) are acquired from the CCD image capturing element. In addition, various information, namely transfer efficiency of the CCD image capturing element, camera sensitivity upon photography, drive frequency of the CCD image capturing element, WB gains of the acquired R, G and B signals, pixel count, internal temperature of camera or temperature of the CCD image capturing element, and CCD color filter array of the CCD image capturing element are acquired. Signal processing on the acquired R, G and B signals is changed according to the acquired information in order to suppress image quality deterioration due to transfer efficiency degradation.
摘要翻译：本发明提供一种能够保持期望的图像质量而不管CCD图像捕获元件的传送效率如何的图像捕获装置。从CCD摄像元件获取R，G，B信号（CCD-RAW数据）。此外，CCD图像拍摄元件的转印效率，摄影时的照相机感光度，CCD摄像元件的驱动频率，所获取的R，G，B信号的WB增益，像素数，照相机的内部温度，获取CCD摄像元件的温度，CCD摄像元件的CCD彩色滤光片阵列。所获取的R，G和B信号的信号处理根据所获取的信息而改变，以便抑制由于传送效率降低导致的图像质量恶化。

5. 发明授权

US5585652A Method and apparatus for real-time background illumination subtraction 失效
标题翻译：用于实时背景照明减法的方法和装置
公开(公告)号：US5585652A
公开(公告)日：1996-12-17
申请号：US328921
申请日：1994-10-25
申请人： Stacy R. Kamasz , Fred S. F. Ma , Michael G. Farrier , Mark P. Bendett
发明人： Stacy R. Kamasz , Fred S. F. Ma , Michael G. Farrier , Mark P. Bendett
IPC分类号： H01L27/148 , H04N5/335 , H04N5/372 , H01L29/768 , H03K23/46 , H04N9/64
CPC分类号： H04N5/335 , H01L27/14831 , H04N3/1575
摘要： The present invention is directed to methods and apparatus for accurately detecting light energy of a signal of interest (e.g., a laser pulse) even when the signal-to-noise ratio is relatively low. The present invention is further directed to accurate detection of a signal of interest even when either or both the signal of interest and background illumination vary across plural pixels of an imaging an array. For example, a signal of interest can be accurately detected even in the presence of pixel response non-uniformity and fixed pattern noise, or when the incident signal of interest is not confined laterally to a single pixel.
摘要翻译：本发明涉及即使当信噪比相对较低时也可准确地检测感兴趣的信号的光能（例如，激光脉冲）的方法和装置。本发明还涉及即使感兴趣的信号和背景照明中的任何一个或两者在成像阵列的多个像素之间变化的情况下，对感兴趣的信号的精确检测。例如，即使在存在像素响应不均匀性和固定模式噪声的情况下，或者当感兴趣的入射信号不侧向限于单个像素时，也可以精确地检测感兴趣的信号。

6. 发明授权

US4574384A Signal transfer system using a charge transfer device 失效
标题翻译：使用电荷转移装置的信号传输系统
公开(公告)号：US4574384A
公开(公告)日：1986-03-04
申请号：US525696
申请日：1983-08-23
申请人： Toshinori Murata , Masafumi Kazumi , Yuji Ito
发明人： Toshinori Murata , Masafumi Kazumi , Yuji Ito
IPC分类号： G11C19/28 , H03K23/46
CPC分类号： G11C19/285
摘要： A charge transfer device has one or more charge injection areas each having an input diffusion layer and two or more input gate electrodes. An input signal is applied to the input diffusion layer, a clock voltage is applied to one of the input gates and an input reference voltage is applied to the other input gate to inject a signal charge proportional to a difference between the input reference voltage and the input signal, and the signal charge is sequentially transferred. A magnitude of the input reference voltage is changed in accordance with a magnitude of a maximum value of the input signal so that transfer of charges which do not contribute to signal component is suppressed and a transfer efficiency is improved.
摘要翻译：电荷转移装置具有一个或多个电荷注入区，每个电荷注入区具有输入扩散层和两个或更多个输入栅电极。将输入信号施加到输入扩散层，将时钟电压施加到输入栅极之一，并且将输入参考电压施加到另一个输入栅极以注入与输入参考电压和输入信号，信号电荷依次传送。输入参考电压的大小根据输入信号的最大值的大小而改变，从而抑制对信号分量无贡献的电荷的传送并提高传送效率。

7. 发明授权

US4314161A Integrated shift register 失效
标题翻译：集成移位寄存器
公开(公告)号：US4314161A
公开(公告)日：1982-02-02
申请号：US53405
申请日：1979-06-29
申请人： Jacob Luscher
发明人： Jacob Luscher
IPC分类号： G04G3/02 , G11C19/18 , H03K21/10 , H03K23/46 , H03K23/66 , G11C19/28
CPC分类号： G04G3/025 , G11C19/186 , H03K21/10 , H03K23/46 , H03K23/66
摘要： The shift register has a very low power consumption. Each cell of the shift register has two stages, each comprising an MOS structure (T.sub.1 -T'.sub.1) which has two principal electrodes (Z.sub.00, Z.sub.1) respectively forming the input (Z.sub.oo) and the output (Z.sub.1) of the stage, and two control electrodes (k.sub.1, k'.sub.1) one of which (k.sub.1) can be connected to a bias source (P) and the other of which (k'.sub.1) is connected to the output electrode (Z.sub.1), and a capacitor (C.sub.1), one plate (Z.sub.1) of which is connected to the said output electrode (Z.sub.1) and the other plate (C.sub.1) of which receives one of two periodic signals .phi..sub.1 (t) and .phi..sub.2 (t) in phase opposition. The register is especially useful in a frequency divider circuit.
摘要翻译：移位寄存器具有非常低的功耗。移位寄存器的每个单元具有两级，每级包括具有分别形成输入（Zoo）和级的输出（Z1）的两个主电极（Z00，Z1）的MOS结构（T1-T'1），以及其中一个（k1）可以连接到偏置源（P）和另一个（k'1）连接到输出电极（Z1）的两个控制电极（k1，k'1）和电容器 C1），其一个板（Z1）连接到所述输出电极（Z1），另一个板（C1）接收相位相反的两个周期信号phi 1（t）和phi 2（t）中的一个。该寄存器在分频器电路中特别有用。

8. 发明授权

US4295056A Integrated frequency divider 失效
标题翻译：集成分频器
公开(公告)号：US4295056A
公开(公告)日：1981-10-13
申请号：US054230
申请日：1979-07-02
申请人： Jacob Luscher
发明人： Jacob Luscher
IPC分类号： G04G3/02 , G11C19/18 , H03K3/356 , H03K23/46 , H03K21/00 , H03K5/13
CPC分类号： G04G3/025 , G11C19/184 , H03K23/46 , H03K3/356017 , H03K3/356069
摘要： The frequency divider allows division of the frequency of two signals in phase opposition .phi..sub.1 (t) and .phi..sub.2 (t). A shift register 10 comprises an assembly of transistors and capacitors which form a plurality of cells connected one after the other, each cell being comprised of two identical stages which are connected in series and are supplied respectively by the periodic signals. Means for detecting particular stages of the register comprise the MOS transistors T.sub.8, T.sub.9, and T.sub.10. Means for producing a signal with a frequency which is a sub-multiple of that of the said periodic signals comprise the transistors T.sub.11 and T.sub.12, the transistor T.sub.13, the capacitor C.sub.7 and the capacitor C.sub.9. The divider is especially suitable for use in quartz oscillator watches.
摘要翻译：分频器允许在相位相反phi 1（t）和phi 2（t）中分离两个信号的频率。移位寄存器10包括晶体管和电容器的组件，其形成多个彼此连接的单元，每个单元由串联连接并分别由周期信号提供的两个相同级构成。用于检测寄存器的特定级的装置包括MOS晶体管T8，T9和T10。用于产生具有所述周期信号的频率的子频率的信号的装置包括晶体管T11和T12，晶体管T13，电容器C7和电容器C9。分频器特别适用于石英振荡器手表。

9. 发明申请

US20100002827A1 SHIFT REGISTER APPARATUS AND METHOD THEREOF 有权
标题翻译：移位寄存器及其方法
公开(公告)号：US20100002827A1
公开(公告)日：2010-01-07
申请号：US12187384
申请日：2008-08-07
申请人： Chih-Jen Shih , Chun-Yuan Hsu , Che-Cheng Kuo , Chun-Kuo Yu
发明人： Chih-Jen Shih , Chun-Yuan Hsu , Che-Cheng Kuo , Chun-Kuo Yu
IPC分类号： H03K23/46
CPC分类号： H03K19/00315 , G09G3/3677 , G09G2310/0286 , G11C19/28
摘要： A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.
摘要翻译：提供一种移位寄存装置及其方法。本发明提供的技术方法利用两个NMOS晶体管来将由移位寄存器装置内的移位寄存器输出的扫描信号的电压电平降低到低电平门电压，其中一个NMOS晶体管由一个控制单元，另一个NMOS晶体管由提供给移位寄存器的时钟信号或反相时钟信号控制。因此，那些NMOS晶体管的阈值电压的移动量趋向于平坦，并且可以促进那些NMOS晶体管的可靠性。此外，由于只需要一个控制单元来配置在每个移位寄存器中，从而可以减少整个移位寄存器装置的布局区域，并且通过本发明也可以实现具有窄帧大小的面板。

10. 发明授权

US07605855B2 Dual sensitivity image sensor 有权
标题翻译：双灵敏度图像传感器
公开(公告)号：US07605855B2
公开(公告)日：2009-10-20
申请号：US11216172
申请日：2005-09-01
申请人： Yibing Michelle Wang , Sandor Barna
发明人： Yibing Michelle Wang , Sandor Barna
IPC分类号： H04N5/335 , H01L27/00 , H03K23/46
CPC分类号： H04N5/35563 , H04N5/3559 , H04N5/374
摘要： A system of taking images of different sensitivities at the same time uses both an image sensor, and an auxiliary part to the image sensor. The image sensor element can be a photogate, and the auxiliary part can be the floating diffusion associated with the photogate. Both the photogate and the floating diffusion accumulate charge. Both are sampled at different times. The floating diffusion provides a lower sensitivity amount of charge than the photogate itself. The system can have a photogate and floating diffusion in each pixel along with a select transistor, a reset transistor, and a follower transistor. All of this circuitry can be formed of CMOS for example. The system can also operate in a column/parallel mode, where each column of the photo sensor array can have a column signal processor which samples and holds the reset signal, the floating diffusion signal and the photogate signal.
摘要翻译：同时拍摄不同灵敏度的图像的系统使用图像传感器和图像传感器的辅助部件。图像传感器元件可以是光栅，并且辅助部件可以是与光栅相关联的浮动扩散。光栅和浮动扩散都积聚电荷。两者都在不同时间采样。浮动扩散提供比光栅本身更低的灵敏度的电荷。该系统可以与选择晶体管，复位晶体管和跟随器晶体管一起在每个像素中具有光栅和浮动扩散。例如，所有这种电路可以由CMOS形成。该系统还可以以列/并行模式工作，其中光传感器阵列的每列可以具有采样并保持复位信号，浮动扩散信号和光栅信号的列信号处理器。

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