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1. 发明公开

US20240251563A1 MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND WRAPPED DATA LINE STRUCTURE 审中-公开
公开(公告)号：US20240251563A1
公开(公告)日：2024-07-25
申请号：US18623956
申请日：2024-04-01
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , Eric S. Carman , Karthik Sarpatwari , Durai Vishak Nirmal Ramaswamy , Richard E. Fackenthal , Haitao Liu
IPC分类号： H10B43/50 , H01L29/10 , H01L29/423
CPC分类号： H10B43/50 , H01L29/1062 , H01L29/42396
摘要： Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

2. 发明授权

US11950426B2 Memory device having 2-transistor vertical memory cell and wrapped data line structure 有权
公开(公告)号：US11950426B2
公开(公告)日：2024-04-02
申请号：US18126679
申请日：2023-03-27
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , Eric S. Carman , Karthik Sarpatwari , Durai Vishak Nirmal Ramaswamy , Richard E Fackenthal , Haitao Liu
IPC分类号： H10B43/50 , H01L29/10 , H01L29/423
CPC分类号： H10B43/50 , H01L29/1062 , H01L29/42396
摘要： Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

3. 发明申请

US20160322422A1 SEMICONDUCTOR DEVICE, MEMORY CIRCUIT, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件，存储器电路，制造半导体器件的方法
公开(公告)号：US20160322422A1
公开(公告)日：2016-11-03
申请号：US15107977
申请日：2014-12-11
申请人： SONY CORPORATION
发明人： TAKASHI YOKOYAMA , TAKU UMEBAYASHI
IPC分类号： H01L27/22 , H01L29/04 , H01L29/768 , H01L43/02 , H01L21/8234 , H01L29/423
CPC分类号： H01L27/228 , H01L21/823406 , H01L21/823487 , H01L27/2454 , H01L29/045 , H01L29/42396 , H01L29/768 , H01L29/7827 , H01L29/7843 , H01L29/7846 , H01L43/02
摘要： A semiconductor device of the technology includes a first diffusion section (22), a second diffusion section (21), a channel section (23), a gate section (24), and a stress application section (31, 32, or 33). In a semiconductor layer (10) having a groove (10A), the first diffusion section (22) is formed at or in the vicinity of a bottom of the groove (10A), the second diffusion section (21) is formed at an upper end of the groove (10A), and the channel section (23) is formed between the first diffusion section (22) and the second diffusion section (21). The gate section (24) is buried in the groove (10A) at a position opposing the channel section (23). The stress application section (31, 32, or 33) applies one of compressive stress and tensile stress to the channel section (23) in a normal direction to the semiconductor layer (10).
摘要翻译：该技术的半导体器件包括第一扩散部分（22），第二扩散部分（21），通道部分（23），栅极部分（24）和应力施加部分（31,32或33）。在具有槽（10A）的半导体层（10）中，第一扩散部（22）形成在槽（10A）的底部或其附近，第二扩散部（21）形成在上部沟槽部分（23）形成在第一扩散部分（22）和第二扩散部分（21）之间。栅极部分（24）在与沟道部分（23）相对的位置处埋在槽（10A）中。应力施加部（31,32,33）在向半导体层（10）的法线方向向通道部（23）施加压缩应力和拉伸应力。

4. 发明授权

US06383834B1 Charge coupled device 有权
标题翻译：电荷耦合器件
公开(公告)号：US06383834B1
公开(公告)日：2002-05-07
申请号：US09222679
申请日：1998-12-29
申请人： Seo Kyu Lee
发明人： Seo Kyu Lee
IPC分类号： H01L27148
CPC分类号： H01L29/42396 , H01L27/14831
摘要： The charge coupled device (CCD) formed according the method of the present invention includes a substrate, at least two photodiodes formed in the substrate and a first insulating layer formed on the substrate. A first transfer gate is formed on a portion of the first insulating layer between the photodiodes. A second insulating layer covers the first transfer gate, and has a projecting portion projecting up from the first transfer gate. The CCD further includes second and third transfer gates disposed over respective sides of the projecting portion of the second insulating layer and the first transfer gate with the second and third transfer gates having a gap therebetween over the projecting portion. A third insulating layer covers the second and third transfer gates, and a fourth transfer gate is formed over a portion of the second and third transfer gates and over the projecting portion of the second insulating layer.
摘要翻译：根据本发明的方法形成的电荷耦合器件（CCD）包括衬底，形成在衬底中的至少两个光电二极管和形成在衬底上的第一绝缘层。第一传输栅极形成在第一绝缘层的光电二极管之间的一部分上。第二绝缘层覆盖第一传输门，并且具有从第一传输门向上突出的突出部分。 CCD还包括设置在第二绝缘层的突出部分的相应侧面上的第二和第三传输门，第一传输门与第二和第三传输门在突出部分之间具有间隙。第三绝缘层覆盖第二和第三传输门，并且第四传输栅极形成在第二和第三传输门的一部分上并在第二绝缘层的突出部分上方。

5. 发明授权

US6136629A Methods for forming a charge coupled devices including buried transmission gates 失效
标题翻译：用于形成包括埋入式传输门的电荷耦合器件的方法
公开(公告)号：US6136629A
公开(公告)日：2000-10-24
申请号：US353739
申请日：1999-07-14
申请人： Jong-Cheol Sin
发明人： Jong-Cheol Sin
IPC分类号： H01L27/146 , H01L27/148 , H01L29/423 , H01L29/768 , H04N5/335 , H04N5/353 , H04N5/359 , H04N5/369 , H04N5/372 , H01L21/00
CPC分类号： H01L29/42396 , H01L27/14812 , H01L27/14831 , H01L29/76808
摘要： A charge coupled device includes a substrate, a photoelectric conversion region, a hole accumulation region, a vertical charge coupled region, and a buried transmission gate region. The substrate includes a surface with a light receiving region and a charge transmission region. The photoelectric conversion region is provided in a substrate beneath the light receiving and charge transmission regions, and the photoelectric conversion region generates a photoelectric signal responsive to light received at the light receiving region of the substrate surface. The hole accumulation region is provided in the substrate between the photoelectric conversion region and the light receiving region of the substrate surface. The vertical charge coupled region is provided in the substrate between the photoelectric conversion region and the charge transmission region of the substrate surface. The buried transmission gate region is provided between the vertical charge coupled region and the photoelectric conversion region. The buried transmission gate region transfers the photoelectric signal from the photoelectric conversion region to a portion of the vertical charge coupled region opposite the substrate surface. Related methods are also disclosed.
摘要翻译：电荷耦合器件包括衬底，光电转换区，空穴累积区，垂直电荷耦合区和掩埋传输门区。衬底包括具有光接收区域和电荷传输区域的表面。光电转换区域设置在光接收和电荷传输区域下方的衬底中，并且光电转换区域响应于在衬底表面的光接收区域处接收的光而产生光电信号。空穴积聚区设置在光电转换区域和基板表面的光接收区域之间的基板中。垂直电荷耦合区域设置在光电转换区域和衬底表面的电荷传输区域之间的衬底中。掩埋传输栅极区域设置在垂直电荷耦合区域和光电转换区域之间。掩埋传输栅极区域将光电信号从光电转换区域传送到与衬底表面相对的垂直电荷耦合区域的一部分。还公开了相关方法。

6. 发明授权

US5793070A Reduction of trapping effects in charge transfer devices 失效
标题翻译：减少电荷转移装置中的捕获效应
公开(公告)号：US5793070A
公开(公告)日：1998-08-11
申请号：US637290
申请日：1996-04-24
申请人： Barry E. Burke
发明人： Barry E. Burke
IPC分类号： H01L21/339 , H01L29/10 , H01L29/423 , H01L27/148 , H01L29/768
CPC分类号： H01L29/66954 , H01L29/1062 , H01L29/42396
摘要： A charge transfer device including a semiconductor substrate, a gate electrode provided in association with the substrate, the gate electrode having a corresponding channel region through which charge is propagated, the channel region having a predetermined potential; and means associated with the channel region for reducing charge trapping and recombination effects. In one aspect of the present invention, the reducing means includes a potential pocket defined within the channel region having a greater potential than the predetermined potential of said channel region. The potential pocket has a width dimension which is less than the corresponding width dimension of the channel region. The potential pocket is positioned in the center of the gate electrode, and is positioned so as to be aligned with a front edge of the gate electrode. The potential pocket is formed by an ion implantation into the semiconductor substrate, a region of an insulating layer having a thickness which differs from the thickness of the remainder of the insulating layer positioned between the gate electrode and the substrate, a second gate electrode positioned adjacent the first gate electrode, or a lightly or undoped second region of a resistive layer disposed adjacent the gate electrode.
摘要翻译：一种电荷转移装置，包括半导体衬底，与衬底相关联地设置的栅电极，栅电极具有通过电荷传播的对应沟道区，沟道区具有预定电位; 以及与通道区域相关联的用于减少电荷捕获和重组效应的装置。在本发明的一个方面，所述还原装置包括限定在所述沟道区内的势阱，所述势阱具有比所述沟道区的预定电位大的电位。潜在的口袋具有小于通道区域的相应宽度尺寸的宽度尺寸。势阱位于栅电极的中心，并且被定位成与栅电极的前边缘对准。通过离子注入到半导体衬底中形成电位袋，绝缘层的区域的厚度不同于位于栅电极和衬底之间的绝缘层的其余部分的厚度，第二栅极位于邻近位置第一栅极电极，或邻近栅电极设置的电阻层的轻度或未掺杂的第二区域。

7. 发明授权

US5637891A Charge coupled device having different insulators 失效
标题翻译：电荷耦合器件具有不同的绝缘子
公开(公告)号：US5637891A
公开(公告)日：1997-06-10
申请号：US706972
申请日：1996-09-03
申请人： Kyung S. Lee
发明人： Kyung S. Lee
IPC分类号： H01L27/148 , H01L29/423
CPC分类号： H01L27/148 , H01L29/42396
摘要： A charged coupled device structure (CCD) and a method for fabricating the CCD structure, which induces a maximum potential distribution difference by utilizing gate insulation films having different physical properties. The charged coupled device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a plurality of first electrodes spaced at fixed intervals over the first insulation layer, a second insulation layer formed only between the plurality of first electrodes and the first insulation layer, a third insulation layer formed over the entire exposed surface of the first electrodes and the first insulation layer, and a plurality of second electrodes formed only on the surface area corresponding to spaces between the plurality of first electrodes. This gate insulation layers having different physical properties induces a maximum potential distribution difference in a semiconductor substrate with a dielectric constant difference between the insulation layers.
摘要翻译：电荷耦合器件结构（CCD）和用于制造CCD结构的方法，其通过利用具有不同物理性质的栅极绝缘膜来诱导最大电位分布差异。所述带电耦合器件包括半导体衬底，形成在所述半导体衬底上的第一绝缘层，在所述第一绝缘层上以固定间隔隔开的多个第一电极，仅在所述多个第一电极和所述第一绝缘层之间形成的第二绝缘层形成在第一电极和第一绝缘层的整个暴露表面上的第三绝缘层，以及仅形成在对应于多个第一电极之间的空间的表面区域上的多个第二电极。具有不同物理性质的栅极绝缘层在绝缘层之间的介电常数差异引起半导体衬底中的最大电位分布差异。

8. 发明授权

US5612555A Full frame solid-state image sensor with altered accumulation potential and method for forming same 失效
标题翻译：具有改变积累电位的全帧固态图像传感器及其形成方法
公开(公告)号：US5612555A
公开(公告)日：1997-03-18
申请号：US408370
申请日：1995-03-22
申请人： Constantine N. Anagnostopoulos
发明人： Constantine N. Anagnostopoulos
IPC分类号： H01L27/148 , H01L29/423 , H01L31/0216 , H01L29/768 , H01L29/792
CPC分类号： H01L31/02161 , H01L27/14831 , H01L29/42396
摘要： In accordance with the invention, a full frame solid-state image sensor of altered accumulation potential comprises a substrate that includes a semiconductor of one conductivity type and has a surface at which is situated a photodetector that comprises a first storage area and a second storage area. The first and second storage areas each comprise a CCD channel of conductivity type opposite to the conductivity type of the semiconductor. A first barrier region separates the first storage area from the second storage area, and a second barrier region separates the second storage area from an adjacent photodetector; the second barrier region is shallower than the first barrier region. Adjacent to one side of the photodetector is a channel stop of the same conductivity type as the semiconductor. A first gate and a second gate each comprising a conductive layer overlie the CCD channel, and positioned between the channel and the conductive layer is an O--N--O dielectric that comprises a first silicon dioxide layer and a second silicon dioxide layer and a silicon nitride layer interposed between the silicon dioxide layers. The silicon nitride layer comprises a trapped electric charge sufficient to alter the accumulation potential by 3 to 4 volts; the trapped electric charge is injected into the silicon nitride layer by applying a stress potential to the first and second gates. Also in accordance with the invention, the silicon nitride layer may be heated simultaneously with the application of the stress potential to the gates.
摘要翻译：根据本发明，具有改变的累积电位的全帧固态图像传感器包括：衬底，其包括一种导电类型的半导体，并且其表面位于包括第一存储区域和第二存储区域的光电检测器。第一和第二存储区域各自包括与半导体的导电类型相反的导电类型的CCD通道。第一屏障区域将第一存储区域与第二存储区域分开，并且第二屏障区域将第二存储区域与相邻的光电检测器分离; 所述第二阻挡区域比所述第一阻挡区域浅。与光电检测器的一侧相邻的是具有与半导体相同导电类型的通道阻挡。每个包括导电层的第一栅极和第二栅极覆盖在CCD沟道上，并且位于沟道和导电层之间的是一个ONO电介质，其包括第一二氧化硅层和第二二氧化硅层以及介于二氧化硅层。氮化硅层包括足以将累积电位改变3至4伏特的俘获电荷; 通过向第一和第二栅极施加应力电势将捕获的电荷注入到氮化硅层中。同样根据本发明，氮化硅层可以同时施加到栅极的应力电位。

9. 发明授权

US5539226A Charge transfer device having an output gate electrode extending over a floating diffusion layer 失效
标题翻译：电荷转移装置具有在浮动扩散层上延伸的输出栅电极
公开(公告)号：US5539226A
公开(公告)日：1996-07-23
申请号：US476028
申请日：1995-06-07
申请人： Seiichi Kawamoto , Yasuhito Maki , Tadakuni Narabu , Masahide Hirama
发明人： Seiichi Kawamoto , Yasuhito Maki , Tadakuni Narabu , Masahide Hirama
IPC分类号： H01L29/423 , H01L29/768 , H01L27/148
CPC分类号： H01L29/42396 , H01L29/76816
摘要： A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon with an insulating film therebetween, a dc voltage being applied to the gate electrode, and an output voltage being applied to the second output gate electrode from the charging detecting circuit.
摘要翻译：一种形成在半导体衬底上的电荷转移装置，包括：形成在半导体衬底上用于转移电荷的电荷转移部分，形成在半导体衬底上的浮置栅极扩散层的浮动栅极，用于累积从电荷转移部分转移的电荷，输出栅极部分，形成在半导体衬底上的电荷转移部分和浮置栅极之间;以及电荷检测电路，电连接到浮置栅极，用于输出与在浮动栅极扩散层中累积的电荷量相对应的电压，栅极部分具有与电荷转移装置相邻的第一输出栅极区域和与浮置栅极扩散层相邻的第二输出栅极区域，第一输出栅极区域具有形成在其间的绝缘膜的第一输出栅电极，第二输出端栅极区域具有第二输出栅极电极在其间形成有绝缘膜，其中直流电压被施加到栅电极，并且输出电压从充电检测电路施加到第二输出栅电极。

10. 发明授权

US5314836A Method of making a single electrode level CCD 失效
标题翻译：制造单电极级CCD的方法
公开(公告)号：US5314836A
公开(公告)日：1994-05-24
申请号：US945073
申请日：1992-09-15
申请人： James P. Lavine
发明人： James P. Lavine
IPC分类号： H01L21/339 , H01L29/423
CPC分类号： H01L29/66954 , H01L29/42396 , Y10S148/111
摘要： The disclosure is directed to a method of forming a CCD with two sets of gate electrodes in a single layer of a conductive material. The method comprises forming a channel region in a body of a semiconductor material along a surface thereof and forming a layer of conductive material over and insulated from the surface of the body. A first masking layer is formed on the conductive layer and spaced strips of polycrystalline silicon are formed on the first masking layer. Using a portion of the spaces between the strips as a mask, impurities of a conductivity type opposite that of the channel region are embedded in the channel region to form spaced barrier regions along the channel region. A layer of silicon dioxide is formed over each of the strips and the spaces between the strips are filled with polycrystalline silicon. The portion of the silicon dioxide layer at one end of each of the strips is etched away to expose a portion of the first masking layer. The exposed portions of the first masking layer are etched away to form grooves through the first masking layer to the conductive layer. The portions of the conductive layer at the bottom of the grooves are then etched away to define the conductive layer into closely spaced gate electrodes.
摘要翻译：本公开涉及一种在导电材料的单层中形成具有两组栅电极的CCD的方法。该方法包括在半导体材料的主体中沿着其表面形成沟道区，并且在主体的表面上形成绝缘层和导电材料。在导电层上形成第一掩模层，并且在第一掩模层上形成间隔开的多晶硅条。使用条带之间的一部分空间作为掩模，导电类型与沟道区域相反的杂质被嵌入在沟道区域中，以形成沿沟道区域的间隔开的阻挡区域。在每个条上形成二氧化硅层，并且条之间的空间填充有多晶硅。每个条带的一端处的二氧化硅层的部分被蚀刻掉以露出第一掩模层的一部分。蚀刻掉第一掩模层的暴露部分，以形成通过第一掩模层到导电层的凹槽。然后蚀刻掉在凹槽底部的导电层的部分，以将导电层限定成紧密隔开的栅电极。

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