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1. 发明授权

US06406975B1 Method for fabricating an air gap shallow trench isolation (STI) structure 失效
标题翻译：制造气隙浅沟槽隔离（STI）结构的方法
公开(公告)号：US06406975B1
公开(公告)日：2002-06-18
申请号：US09721718
申请日：2000-11-27
申请人： Victor Seng Keong Lim , Young-Way Teh , Ting-Cheong Ang , Alex See , Yong Kong Siew
发明人： Victor Seng Keong Lim , Young-Way Teh , Ting-Cheong Ang , Alex See , Yong Kong Siew
IPC分类号： H01L2176
CPC分类号： H01L21/764 , H01L21/76232
摘要： A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.
摘要翻译：制造具有气隙的浅沟槽隔离（STI）的方法，该气隙是通过将有机填充材料分解成盖层形成的。衬底层和阻挡层形成在衬底上。衬垫层和阻挡层被图案化以形成沟槽开口。我们通过蚀刻通过沟槽开口在衬底中形成沟槽。第一衬里层形成在沟槽的侧壁上。在阻挡层和第一衬里层上的第二衬里层。在第二衬垫层上形成填充材料以填充沟槽。在重要的步骤中，覆盖层沉积在填充材料和第二衬里层上。对填充材料进行等离子体处理并加热以使填充材料汽化，使得填充材料通过盖层扩散以形成间隙。绝缘层沉积在覆盖层上。绝缘层被平坦化。去除阻挡层。

2. 发明授权

US06380106B1 Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures 有权
标题翻译：制造气隙金属化方案的方法，其减少互连结构的金属间电容
公开(公告)号：US06380106B1
公开(公告)日：2002-04-30
申请号：US09721719
申请日：2000-11-27
申请人： Seng Keong Victor Lim , Young-way Teh , Ting-Cheong Ang , Alex See , Yong Kong Siew
发明人： Seng Keong Victor Lim , Young-way Teh , Ting-Cheong Ang , Alex See , Yong Kong Siew
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02274 , H01L21/31608 , H01L21/7682
摘要： A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material. The permeable dielectric layer has a property of allowing decomposed gas phase filler material to diffuse through. In another critical step, we vaporize the filler material changing the filler material into a vapor phase filler material. The vapor phase filler material diffuses through the permeable dielectric layer to form a gap between the spaced conductive lines. An insulating layer is formed over the permeable dielectric layer.
摘要翻译：一种制造具有通过汽化填料聚合物材料形成气隙的金属化方案的方法。填充材料被临界可渗透的介电层覆盖。该方法开始于在半导体结构上形成间隔的导线。间隔的导线具有顶表面。在间隔的导线和半导体结构之上形成填充材料。填充材料优选由选自聚丙二醇（PPG），聚丁二烯（PB）聚乙二醇（PEG），氟化无定形碳和聚己内酯二醇（PCL）组成的组中的材料组成，并且通过旋涂工艺或 CVD工艺。我们回蚀填充材料以暴露间隔的导线的顶表面。接下来，将半导体结构加载到HDPCVD室中。在关键步骤中，在填充材料上形成可渗透介电层。可渗透介电层具有允许分解的气相填充材料扩散通过的性质。在另一个关键步骤中，我们将填充材料蒸发成将填料材料变成气相填料。气相填充材料通过可渗透的介电层扩散以在间隔的导线之间形成间隙。在可渗透介电层上形成绝缘层。

3. 发明申请

US20090315115A1 Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement 审中-公开
标题翻译：用于浅沟槽隔离（STI）形成和用于晶体管性能增强的应力的植入
公开(公告)号：US20090315115A1
公开(公告)日：2009-12-24
申请号：US12214854
申请日：2008-06-23
申请人： Beichao Zhang , Johnny Widodo , Juan Boon Tan , Yong Kong Siew , Fan Zhang , Haifeng Sheng , Wenhe Lin , Young Way Teh , Jinping Liu , Vincent Ho , Liang Choo Hsia
发明人： Beichao Zhang , Johnny Widodo , Juan Boon Tan , Yong Kong Siew , Fan Zhang , Haifeng Sheng , Wenhe Lin , Young Way Teh , Jinping Liu , Vincent Ho , Liang Choo Hsia
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823481 , H01L21/76224 , H01L29/7846
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.
摘要翻译：制造半导体器件的方法（和半导体器件）通过在STI区域中注入离子来提供浅沟槽隔离（STI）结构或区域。在植入之后，区域（衬底材料和不同元素的离子）进行热退火，产生用于隔离两个相邻的场效应晶体管（FET）的电介质材料。这消除了去除衬底材料以形成沟槽并用电介质材料重新填充沟槽的常规步骤。将氮离子注入到邻近p型FET的STI区域中，对晶体管沟道区域施加压缩应力以增强晶体管性能。将氧离子注入到与n型FET相邻的STI区域中，对晶体管沟道区域施加拉伸应力以增强晶体管性能。

4. 发明授权

US08519445B2 Poly profile engineering to modulate spacer induced stress for device enhancement 有权
标题翻译：聚轮廓工程用于调制间隔物诱发的应力用于器件增强
公开(公告)号：US08519445B2
公开(公告)日：2013-08-27
申请号：US13182455
申请日：2011-07-14
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L27/10 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

5. 发明授权

US07993997B2 Poly profile engineering to modulate spacer induced stress for device enhancement 有权
标题翻译：聚轮廓工程用于调制间隔物诱发的应力用于器件增强
公开(公告)号：US07993997B2
公开(公告)日：2011-08-09
申请号：US11865563
申请日：2007-10-01
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

6. 发明申请

US20090085122A1 POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT 有权
标题翻译： POLY PROFILE工程来调节间隔器感应应变的设备增强
公开(公告)号：US20090085122A1
公开(公告)日：2009-04-02
申请号：US11865563
申请日：2007-10-01
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

7. 发明授权

US07833900B2 Interconnections for integrated circuits including reducing an overburden and annealing 有权
标题翻译：集成电路的互连，包括减少覆盖层和退火
公开(公告)号：US07833900B2
公开(公告)日：2010-11-16
申请号：US12048223
申请日：2008-03-14
申请人： Lup San Leong , Yong Kong Siew , Liang Choo Hsia
发明人： Lup San Leong , Yong Kong Siew , Liang Choo Hsia
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/302
CPC分类号： H01L21/76877
摘要： The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.
摘要翻译：本发明公开了一种在其上设置有半导体器件的半导体衬底上制造集成电路的方法，包括以下步骤：形成具有所需厚度的覆盖层的铜层，在铜层上形成惰性金属层，退火铜层并去除惰性金属层。

8. 发明授权

US07524755B2 Entire encapsulation of Cu interconnects using self-aligned CuSiN film 有权
标题翻译：使用自对准CuSiN膜的Cu互连的全封装
公开(公告)号：US07524755B2
公开(公告)日：2009-04-28
申请号：US11358934
申请日：2006-02-22
申请人： Johnny Widodo , Bei Chao Zhang , Tong Qing Chen , Yong Kong Siew , Fan Zhang , San Leong Liew , John Sudijono , Liang Choo Hsia
发明人： Johnny Widodo , Bei Chao Zhang , Tong Qing Chen , Yong Kong Siew , Fan Zhang , San Leong Liew , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L24/03 , H01L24/05 , H01L2224/05073 , H01L2224/05546 , H01L2224/05647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/14 , H01L2924/01039 , H01L2924/00
摘要： A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.
摘要翻译：形成用于互连的CuSiN构成的阻挡层和盖的方法。我们在半导体结构上的电介质层中提供互连开口。通过与第一铜层反应，在互连开口的侧壁和底部上形成CuSiN阻挡层。然后，我们在填充互连开口的CuSiN层上形成互连。我们可以在互连的顶部表面上形成CuSiN覆盖层。

9. 发明授权

US07670946B2 Methods to eliminate contact plug sidewall slit 有权
标题翻译：消除接触塞侧壁狭缝的方法
公开(公告)号：US07670946B2
公开(公告)日：2010-03-02
申请号：US11434343
申请日：2006-05-15
申请人： Yong Kong Siew , Beichao Zhang
发明人： Yong Kong Siew , Beichao Zhang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , H01L21/02074 , H01L21/7684 , H01L21/76852 , H01L21/76865 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method to form a barrier layer and contact plug using a touch up RIE. In a first embodiment, we form a first barrier layer over the dielectric layer and the substrate in the contact hole. The first barrier layer is comprised of Ta. A second barrier layer is formed over the first barrier layer. The second barrier layer is comprised of TaN or WN. We planarize a first conductive layer to form a first contact plug in the contact hole. We reactive ion etch (e.g., W touch up etch) the top surfaces using a Cl and B containing etch. Because of the composition of the barrier layers and RIE etch chemistry, the barrier layers are not significantly etched selectively to the dielectric layer. In a second embodiment, a barrier film is comprised of WN.
摘要翻译：使用接触式RIE形成阻挡层和接触塞的方法。在第一实施例中，我们在电介质层和接触孔中的衬底之间形成第一阻挡层。第一阻挡层由Ta构成。在第一阻挡层上形成第二阻挡层。第二阻挡层由TaN或WN构成。我们平面化第一导电层以在接触孔中形成第一接触塞。我们使用含Cl和B的蚀刻反应离子蚀刻（例如，W触摸上蚀刻）顶表面。由于阻挡层的组成和RIE蚀刻化学，阻挡层没有被有选择地蚀刻到电介质层。在第二实施例中，阻挡膜由WN构成。

10. 发明授权

US07947604B2 Method for corrosion prevention during planarization 有权
标题翻译：平面化期间的防腐蚀方法
公开(公告)号：US07947604B2
公开(公告)日：2011-05-24
申请号：US12019647
申请日：2008-01-25
申请人： Fan Zhang , Lup San Leong , Yong Kong Siew , Bei Chao Zhang
发明人： Fan Zhang , Lup San Leong , Yong Kong Siew , Bei Chao Zhang
IPC分类号： H01L21/302
CPC分类号： B24B37/042 , B24B37/046
摘要： The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.
摘要翻译：本发明涉及在平坦化或抛光过程中减少或完全防止Cu腐蚀。在本发明的一个方面中，RF信号用于在抛光之后在晶片表面前建立负偏压以消除Cu +或Cu 2+迁移。在本发明的另一方面，使用DC电压电源来建立负偏压。

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