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1. 发明授权

US07833900B2 Interconnections for integrated circuits including reducing an overburden and annealing 有权
标题翻译：集成电路的互连，包括减少覆盖层和退火
公开(公告)号：US07833900B2
公开(公告)日：2010-11-16
申请号：US12048223
申请日：2008-03-14
申请人： Lup San Leong , Yong Kong Siew , Liang Choo Hsia
发明人： Lup San Leong , Yong Kong Siew , Liang Choo Hsia
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/302
CPC分类号： H01L21/76877
摘要： The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.
摘要翻译：本发明公开了一种在其上设置有半导体器件的半导体衬底上制造集成电路的方法，包括以下步骤：形成具有所需厚度的覆盖层的铜层，在铜层上形成惰性金属层，退火铜层并去除惰性金属层。

2. 发明申请

US20090315115A1 Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement 审中-公开
标题翻译：用于浅沟槽隔离（STI）形成和用于晶体管性能增强的应力的植入
公开(公告)号：US20090315115A1
公开(公告)日：2009-12-24
申请号：US12214854
申请日：2008-06-23
申请人： Beichao Zhang , Johnny Widodo , Juan Boon Tan , Yong Kong Siew , Fan Zhang , Haifeng Sheng , Wenhe Lin , Young Way Teh , Jinping Liu , Vincent Ho , Liang Choo Hsia
发明人： Beichao Zhang , Johnny Widodo , Juan Boon Tan , Yong Kong Siew , Fan Zhang , Haifeng Sheng , Wenhe Lin , Young Way Teh , Jinping Liu , Vincent Ho , Liang Choo Hsia
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823481 , H01L21/76224 , H01L29/7846
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.
摘要翻译：制造半导体器件的方法（和半导体器件）通过在STI区域中注入离子来提供浅沟槽隔离（STI）结构或区域。在植入之后，区域（衬底材料和不同元素的离子）进行热退火，产生用于隔离两个相邻的场效应晶体管（FET）的电介质材料。这消除了去除衬底材料以形成沟槽并用电介质材料重新填充沟槽的常规步骤。将氮离子注入到邻近p型FET的STI区域中，对晶体管沟道区域施加压缩应力以增强晶体管性能。将氧离子注入到与n型FET相邻的STI区域中，对晶体管沟道区域施加拉伸应力以增强晶体管性能。

3. 发明授权

US07524755B2 Entire encapsulation of Cu interconnects using self-aligned CuSiN film 有权
标题翻译：使用自对准CuSiN膜的Cu互连的全封装
公开(公告)号：US07524755B2
公开(公告)日：2009-04-28
申请号：US11358934
申请日：2006-02-22
申请人： Johnny Widodo , Bei Chao Zhang , Tong Qing Chen , Yong Kong Siew , Fan Zhang , San Leong Liew , John Sudijono , Liang Choo Hsia
发明人： Johnny Widodo , Bei Chao Zhang , Tong Qing Chen , Yong Kong Siew , Fan Zhang , San Leong Liew , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L24/03 , H01L24/05 , H01L2224/05073 , H01L2224/05546 , H01L2224/05647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/14 , H01L2924/01039 , H01L2924/00
摘要： A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.
摘要翻译：形成用于互连的CuSiN构成的阻挡层和盖的方法。我们在半导体结构上的电介质层中提供互连开口。通过与第一铜层反应，在互连开口的侧壁和底部上形成CuSiN阻挡层。然后，我们在填充互连开口的CuSiN层上形成互连。我们可以在互连的顶部表面上形成CuSiN覆盖层。

4. 发明申请

US20110266628A1 POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT 有权
标题翻译： POLY PROFILE工程来调节间隔器感应应变的设备增强
公开(公告)号：US20110266628A1
公开(公告)日：2011-11-03
申请号：US13182455
申请日：2011-07-14
申请人： Vincent HO , Wenhe LIN , Young Way TEH , Yong Kong SIEW , Bei Chao ZHANG , Fan ZHANG , Haifeng SHENG , Juan Boon TAN
发明人： Vincent HO , Wenhe LIN , Young Way TEH , Yong Kong SIEW , Bei Chao ZHANG , Fan ZHANG , Haifeng SHENG , Juan Boon TAN
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

5. 发明授权

US07993997B2 Poly profile engineering to modulate spacer induced stress for device enhancement 有权
标题翻译：聚轮廓工程用于调制间隔物诱发的应力用于器件增强
公开(公告)号：US07993997B2
公开(公告)日：2011-08-09
申请号：US11865563
申请日：2007-10-01
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

6. 发明申请

US20090191792A1 METHOD FOR CORROSION PREVENTION DURING PLANARIZATION 有权
标题翻译：平面预防腐蚀预防方法
公开(公告)号：US20090191792A1
公开(公告)日：2009-07-30
申请号：US12019647
申请日：2008-01-25
申请人： Fan ZHANG , Lup San LEONG , Yong Kong SIEW , Bei Chao ZHANG
发明人： Fan ZHANG , Lup San LEONG , Yong Kong SIEW , Bei Chao ZHANG
IPC分类号： B24B1/00
CPC分类号： B24B37/042 , B24B37/046
摘要： The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.
摘要翻译：本发明涉及在平坦化或抛光过程中减少或完全防止Cu腐蚀。在本发明的一个方面中，RF信号用于在抛光之后在晶片表面前建立负偏压以消除Cu +或Cu 2+迁移。在本发明的另一方面，使用DC电压电源来建立负偏压。

7. 发明申请

US20090085122A1 POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT 有权
标题翻译： POLY PROFILE工程来调节间隔器感应应变的设备增强
公开(公告)号：US20090085122A1
公开(公告)日：2009-04-02
申请号：US11865563
申请日：2007-10-01
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

8. 发明授权

US07247555B2 Method to control dual damascene trench etch profile and trench depth uniformity 有权
标题翻译：控制双镶嵌沟槽蚀刻轮廓和沟槽深度均匀性的方法
公开(公告)号：US07247555B2
公开(公告)日：2007-07-24
申请号：US10767292
申请日：2004-01-29
申请人： Hai Cong , Yong Kong Siew , Liang Choo Hsia
发明人： Hai Cong , Yong Kong Siew , Liang Choo Hsia
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76808
摘要： A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. Via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. The dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without any fencing or faceting. The present method solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.
摘要翻译：一种在双镶嵌沟槽和通孔蚀刻工艺中形成沟槽开口的方法，其通过使用称为双层的双组分硬掩模层在不同的金属间电介质IMD之间，以解决双镶嵌图案化问题，例如栅栏和子层螺旋形成。通过在双镶嵌处理中的首次图案化是铜后端（BEOL）集成的主要集成方案之一。通过第一双镶嵌方案通常使用沉积在金属间电介质（IMD）膜堆叠顶部上的硬掩模层。双镶嵌沟槽蚀刻需要在蚀刻后跨晶片的均匀沟槽深度。此外，通过顶角型材需要维护良好，没有任何围栏或小面。本方法通过使用直接沉积在金属间电介质（IMD）膜堆叠的顶部上的双组分硬掩模层来解决这些问题。

9. 发明授权

US6121135A Modified buried contact process for IC device fabrication 有权
标题翻译：用于IC器件制造的改进的埋入接触工艺
公开(公告)号：US6121135A
公开(公告)日：2000-09-19
申请号：US314591
申请日：1999-05-19
申请人： Yong Kong Siew , Lap Chan
发明人： Yong Kong Siew , Lap Chan
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76895
摘要： A new method of forming a butted contact and a buried contact having low contact resistance in the fabrication of integrated circuits is described. A first layer of polysilicon is deposited over a gate silicon oxide layer over the surface of a semiconductor substrate. The first polysilicon and gate oxide layers are etched away to provide an opening to the substrate. A second polysilicon layer is deposited over the first polysilicon layer and the substrate within the opening and doped whereby the buried contact junction is formed in the substrate underlying the doped second polysilicon layer. The second polysilicon layer is planarized. The first and second polysilicon layers are etched away to provide an opening overlying a portion of the buried contact junction wherein a trench is etched into the substrate where the substrate is not covered by the gate oxide layer. An oxide layer is deposited over the second polysilicon layer and within the trench. The oxide layer is etched away wherein the trench and a portion of the second polysilicon layer overlying the buried contact junction and adjacent to the trench are exposed and whereby the oxide is removed from the trench. A third polysilicon layer is deposited over the oxide layer and the second polysilicon layer and the trench exposed within the opening. The third polysilicon layer is patterned to form a butted contact with the second polysilicon layer exposed within the opening.
摘要翻译：描述了在集成电路的制造中形成具有低接触电阻的对接触点和埋入触点的新方法。第一层多晶硅沉积在半导体衬底的表面上的栅极氧化硅层上。蚀刻掉第一多晶硅和栅极氧化物层以提供对衬底的开口。第二多晶硅层沉积在开口内的第一多晶硅层和衬底上，并且被掺杂，由此在掺杂的第二多晶硅层下面的衬底中形成掩埋接触结。第二多晶硅层被平坦化。蚀刻掉第一和第二多晶硅层以提供覆盖掩埋接触结的一部分的开口，其中将沟槽蚀刻到衬底中，其中衬底未被栅极氧化物层覆盖。氧化物层沉积在第二多晶硅层上并在沟槽内。蚀刻掉氧化物层，其中将沟槽和覆盖在掩埋接触结上并与沟槽相邻的第二多晶硅层的一部分被暴露，从而从沟槽去除氧化物。第三多晶硅层沉积在氧化物层上，第二多晶硅层和暴露在开口内的沟槽。图案化第三多晶硅层以与在开口内暴露的第二多晶硅层形成对接接触。

10. 发明授权

US07947604B2 Method for corrosion prevention during planarization 有权
标题翻译：平面化期间的防腐蚀方法
公开(公告)号：US07947604B2
公开(公告)日：2011-05-24
申请号：US12019647
申请日：2008-01-25
申请人： Fan Zhang , Lup San Leong , Yong Kong Siew , Bei Chao Zhang
发明人： Fan Zhang , Lup San Leong , Yong Kong Siew , Bei Chao Zhang
IPC分类号： H01L21/302
CPC分类号： B24B37/042 , B24B37/046
摘要： The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.
摘要翻译：本发明涉及在平坦化或抛光过程中减少或完全防止Cu腐蚀。在本发明的一个方面中，RF信号用于在抛光之后在晶片表面前建立负偏压以消除Cu +或Cu 2+迁移。在本发明的另一方面，使用DC电压电源来建立负偏压。

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