专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07524755B2 Entire encapsulation of Cu interconnects using self-aligned CuSiN film 有权
标题翻译：使用自对准CuSiN膜的Cu互连的全封装
公开(公告)号：US07524755B2
公开(公告)日：2009-04-28
申请号：US11358934
申请日：2006-02-22
申请人： Johnny Widodo , Bei Chao Zhang , Tong Qing Chen , Yong Kong Siew , Fan Zhang , San Leong Liew , John Sudijono , Liang Choo Hsia
发明人： Johnny Widodo , Bei Chao Zhang , Tong Qing Chen , Yong Kong Siew , Fan Zhang , San Leong Liew , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L24/03 , H01L24/05 , H01L2224/05073 , H01L2224/05546 , H01L2224/05647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/14 , H01L2924/01039 , H01L2924/00
摘要： A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.
摘要翻译：形成用于互连的CuSiN构成的阻挡层和盖的方法。我们在半导体结构上的电介质层中提供互连开口。通过与第一铜层反应，在互连开口的侧壁和底部上形成CuSiN阻挡层。然后，我们在填充互连开口的CuSiN层上形成互连。我们可以在互连的顶部表面上形成CuSiN覆盖层。

2. 发明授权

US07294241B2 Method to form alpha phase Ta and its application to IC manufacturing 有权
标题翻译：形成α相Ta的方法及其在IC制造中的应用
公开(公告)号：US07294241B2
公开(公告)日：2007-11-13
申请号：US10336271
申请日：2003-01-03
申请人： Chim Seng Seet , Bei Chao Zhang , San Leong Liew , John Sudijono , Lai Lin Clare Yong
发明人： Chim Seng Seet , Bei Chao Zhang , San Leong Liew , John Sudijono , Lai Lin Clare Yong
IPC分类号： C23C14/34 , H01L21/44
CPC分类号： H01L21/76843 , C23C14/165 , C23C14/541 , H01L21/2855 , H01L21/76846 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05001 , H01L2224/0554 , H01L2224/13022 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/351 , Y10T428/12674 , Y10T428/12819 , Y10T428/12903 , H01L2924/00
摘要： A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.
摘要翻译：将由Al相Ta组成的Ta层溅射在Cu层上的方法。一个实施方案包括在低于200℃的衬底温度下在Cu表面上的Ta溅射沉积。另一个实施方案在Ta层溅射沉积之前具有在低于100℃的温度下的预冷却步骤。在另一个非限制性示例性实施例中，在钽溅射之前执行包括惰性气体溅射的预清洁步骤。另一非限制性示例实施例提供一种半导体结构，包括：半导体结构; 半导体结构上的铜层; 铜层上的钽层; 钽层包括α相Ta; 钽层上的金属层。

3. 发明授权

US08177993B2 Apparatus and methods for cleaning and drying of wafers 有权
标题翻译：用于清洗和干燥晶片的装置和方法
公开(公告)号：US08177993B2
公开(公告)日：2012-05-15
申请号：US11556696
申请日：2006-11-05
申请人： Boon Meng Seah , Bei Chao Zhang , Raymond Joy , Shao Beng Law , John Sudijono , Liang Choo Hsia
发明人： Boon Meng Seah , Bei Chao Zhang , Raymond Joy , Shao Beng Law , John Sudijono , Liang Choo Hsia
IPC分类号： B44C1/22
CPC分类号： H01L21/67028 , H01L21/67051 , H01L21/6708
摘要： An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.
摘要翻译：用于蚀刻和清洁衬底的第一示例性方法和装置包括具有第一歧管和第二歧管的装置。第一歧管具有用于将化学品分配到基底上的多个喷嘴。第二歧管连接到真空源和/或干燥空气/气体源。第二示例性实施例是晶片清洁装置和方法，其使用具有毛细管喷嘴和液体毛细管喷流的歧管来清洁基底。

4. 发明申请

US20080105653A1 Apparatus and methods for Cleaning and Drying of wafers 有权
标题翻译：用于清洁和干燥晶片的装置和方法
公开(公告)号：US20080105653A1
公开(公告)日：2008-05-08
申请号：US11556696
申请日：2006-11-05
申请人： Boon Meng Seah , Bei Chao Zhang , Raymond Joy , Shao Beng Law , John Sudijono , Liang Choo Hsia
发明人： Boon Meng Seah , Bei Chao Zhang , Raymond Joy , Shao Beng Law , John Sudijono , Liang Choo Hsia
IPC分类号： B05B13/04 , B05B1/14 , B08B3/08 , B44C1/22
CPC分类号： H01L21/67028 , H01L21/67051 , H01L21/6708
摘要： An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.
摘要翻译：用于蚀刻和清洁衬底的第一示例性方法和装置包括具有第一歧管和第二歧管的装置。第一歧管具有用于将化学品分配到基底上的多个喷嘴。第二歧管连接到真空源和/或干燥空气/气体源。第二示例性实施例是晶片清洁装置和方法，其使用具有毛细管喷嘴和液体毛细管喷流的歧管来清洁基底。

5. 发明申请

US20070197023A1 Entire encapsulation of Cu interconnects using self-aligned CuSiN film 有权
标题翻译：使用自对准CuSiN膜的Cu互连的全封装
公开(公告)号：US20070197023A1
公开(公告)日：2007-08-23
申请号：US11358934
申请日：2006-02-22
申请人： Johnny Widodo , Bei Zhang , Tong Chen , Yong Siew , Fan Zhang , San Liew , John Sudijono , Liang Hsia
发明人： Johnny Widodo , Bei Zhang , Tong Chen , Yong Siew , Fan Zhang , San Liew , John Sudijono , Liang Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L24/03 , H01L24/05 , H01L2224/05073 , H01L2224/05546 , H01L2224/05647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/14 , H01L2924/01039 , H01L2924/00
摘要： A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.
摘要翻译：形成用于互连的CuSiN构成的阻挡层和盖的方法。我们在半导体结构上的电介质层中提供互连开口。通过与第一铜层反应，在互连开口的侧壁和底部上形成CuSiN阻挡层。然后，我们在填充互连开口的CuSiN层上形成互连。我们可以在互连的顶部表面上形成CuSiN覆盖层。

6. 发明申请

US20070281410A1 Spacer-less low-k dielectric processes 有权
标题翻译：无隔离低k介电过程
公开(公告)号：US20070281410A1
公开(公告)日：2007-12-06
申请号：US11447565
申请日：2006-06-05
申请人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
发明人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/8234
CPC分类号： H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
摘要翻译：第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。这用于减小寄生电容。此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。示例性实施例可以提高设备性能，例如边缘振荡器的性能。

7. 发明授权

US07999325B2 Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS 有权
标题翻译：腐蚀后去除间隔物的方法，以增强接触蚀刻停止衬垫在MOS上的应力
公开(公告)号：US07999325B2
公开(公告)日：2011-08-16
申请号：US12241073
申请日：2008-09-30
申请人： Young Way Teh , Yong Meng Lee , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , John Sudijono , Hui Peng Koh , Liang Choo Hsia
发明人： Young Way Teh , Yong Meng Lee , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , John Sudijono , Hui Peng Koh , Liang Choo Hsia
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823864
摘要： An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
摘要翻译：从NMOS晶体管的栅极去除间隔物的示例性过程。在NMOS和PMOS晶体管和衬底上形成应力产生层。在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。应力产生层优选为拉伸氮化物层。应力产生层优选为接触蚀刻停止衬层。在一个实施例中，在形成应力产生层之前，栅极，源极和漏极区域之前具有硅化物层。该实施例改善了NMOS晶体管的性能。

8. 发明授权

US06787452B2 Use of amorphous carbon as a removable ARC material for dual damascene fabrication 失效
标题翻译：使用无定形碳作为可拆卸的ARC材料进行双镶嵌制造
公开(公告)号：US06787452B2
公开(公告)日：2004-09-07
申请号：US10290629
申请日：2002-11-08
申请人： John Sudijono , Liang Choo Hsia , Liu Huang
发明人： John Sudijono , Liang Choo Hsia , Liu Huang
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/0276 , H01L21/31144 , H01L21/3146 , H01L21/76802 , Y10S438/952
摘要： An improved method of controlling a critical dimension during a photoresist patterning process is provided which can be applied to forming vias and trenches in a dual damascene structure. An amorphous carbon ARC is deposited on a substrate by a PECVD method. Preferred conditions are a RF power from 50 to 500 Watts, a bias of 500 to 2000 Watts, a chamber and substrate temperature of 300° C. to 400° C. with a trimethylsilane flow rate of 50 to 200 sccm, a helium flow rate of 100 to 1000 sccm, and an argon flow rate of 50 to 200 sccm. Argon plasma imparts an amorphous character to the film. The refractive index (n and k) can be tuned for a variety of photoresist applications including 193 nm, 248 nm, and 365 nm exposures. The &agr;-carbon layer provides a high etch selectivity relative to oxide and can be easily removed with a plasma etch.
摘要翻译：提供了一种在光致抗蚀剂图案化工艺期间控制临界尺寸的改进方法，其可以应用于在双镶嵌结构中形成通路和沟槽。通过PECVD方法将非晶碳ARC沉积在衬底上。优选的条件是50至500瓦的RF功率，500至2000瓦特的偏压，室和基板温度为300℃至400℃，三甲基硅烷流速为50至200sccm，氦流量为100〜1000sccm，氩气流量为50〜200sccm。氩等离子体为电影赋予无定形特征。折射率（n和k）可以针对各种光刻胶应用进行调整，包括193 nm，248 nm和365 nm曝光。 α碳层相对于氧化物提供高蚀刻选择性，并且可以容易地用等离子体蚀刻去除。

9. 发明授权

US07615427B2 Spacer-less low-k dielectric processes 有权
标题翻译：无隔离低k介电过程
公开(公告)号：US07615427B2
公开(公告)日：2009-11-10
申请号：US11447565
申请日：2006-06-05
申请人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
发明人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
摘要翻译：第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。这用于减小寄生电容。此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。示例性实施例可以提高设备性能，例如边缘振荡器的性能。

10. 发明申请

US20080315317A1 SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS 审中-公开
标题翻译：具有补充应变通道的半导体系统
公开(公告)号：US20080315317A1
公开(公告)日：2008-12-25
申请号：US11767449
申请日：2007-06-22
申请人： Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Khee Yong Lim , Young Way Teh , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang-Choo Hsia
发明人： Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Khee Yong Lim , Young Way Teh , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang-Choo Hsia
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/31155 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/66606 , H01L29/7843
摘要： A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.
摘要翻译：提供一种半导体系统，包括提供半导体衬底; 在半导体衬底中形成PMOS和NMOS晶体管; 在半导体衬底上形成拉伸应变层; 并放宽PMOS晶体管周围的拉伸应变层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式