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    • 4. 发明授权
    • Polishing apparatus and method for forming an integrated circuit
    • 抛光装置和形成集成电路的方法
    • US06376378B1
    • 2002-04-23
    • US09415364
    • 1999-10-08
    • Feng ChenLup San LeongCharles Lin
    • Feng ChenLup San LeongCharles Lin
    • H01L21461
    • B24B37/042B24B37/20H01L21/31053H01L21/3212
    • In one embodiment, a dielectric layer (144, 156) overlying a semiconductor substrate (28) is uniformly polished. During polishing, the perimeter (32) of the semiconductor substrate (28) overlies a peripheral region (16, 48, 66, 86, 120) of a polishing pad (6, 42, 60, 80, 100) and an edge portion (36) of the front surface of semiconductor substrate (28) is not in contact with the front surface (18, 50, 68, 88, 122) of the polishing pad (6, 42, 60, 80, 100), in the peripheral region (16, 48, 66, 86, 120). As a result, the polishing rate at the edge portion (36) of the semiconductor substrate (28) is reduced, and the semiconductor substrate (28) is polished with improved center to edge uniformity. Since the semiconductor substrate (28) is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion (36) of the semiconductor substrate (28) are not over polished.
    • 在一个实施例中,覆盖半导体衬底(28)的电介质层(144,156)被均匀抛光。 在抛光期间,半导体衬底(28)的周边(32)覆盖在抛光垫(6,42,60,80,100)和边缘部分(16,48,66,101)周边区域 半导体衬底(28)的前表面的表面(36)不与抛光垫(6,42,60,80,100)的前表面(18,50,68,88,100)接触, 区域(16,48,66,86,120)。 结果,半导体衬底(28)的边缘部分(36)处的抛光速率降低,并且半导体衬底(28)以改善的中心到边缘均匀性被抛光。 由于半导体基板(28)以改善的中心到边缘均匀性被抛光,所以由于位于半导体基板(28)的边缘部分(36)内的模具没有被过度抛光,所以提高了模具的产量。