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1. 发明授权

US07833900B2 Interconnections for integrated circuits including reducing an overburden and annealing 有权
标题翻译：集成电路的互连，包括减少覆盖层和退火
公开(公告)号：US07833900B2
公开(公告)日：2010-11-16
申请号：US12048223
申请日：2008-03-14
申请人： Lup San Leong , Yong Kong Siew , Liang Choo Hsia
发明人： Lup San Leong , Yong Kong Siew , Liang Choo Hsia
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/302
CPC分类号： H01L21/76877
摘要： The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.
摘要翻译：本发明公开了一种在其上设置有半导体器件的半导体衬底上制造集成电路的方法，包括以下步骤：形成具有所需厚度的覆盖层的铜层，在铜层上形成惰性金属层，退火铜层并去除惰性金属层。

2. 发明申请

US20090233441A1 INTERCONNECTIONS FOR INTEGRATED CIRCUITS 有权
标题翻译：集成电路互连
公开(公告)号：US20090233441A1
公开(公告)日：2009-09-17
申请号：US12048223
申请日：2008-03-14
申请人： Lup San Leong , Yong Kong Siew , Liang Choo Hsia
发明人： Lup San Leong , Yong Kong Siew , Liang Choo Hsia
IPC分类号： H01L21/44 , C23C16/44 , B05C3/02
CPC分类号： H01L21/76877
摘要： The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.
摘要翻译：本发明公开了一种在其上设置有半导体器件的半导体衬底上制造集成电路的方法，包括以下步骤：形成具有所需厚度的覆盖层的铜层，在铜层上形成惰性金属层，退火铜层并去除惰性金属层。

3. 发明授权

US07947604B2 Method for corrosion prevention during planarization 有权
标题翻译：平面化期间的防腐蚀方法
公开(公告)号：US07947604B2
公开(公告)日：2011-05-24
申请号：US12019647
申请日：2008-01-25
申请人： Fan Zhang , Lup San Leong , Yong Kong Siew , Bei Chao Zhang
发明人： Fan Zhang , Lup San Leong , Yong Kong Siew , Bei Chao Zhang
IPC分类号： H01L21/302
CPC分类号： B24B37/042 , B24B37/046
摘要： The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.
摘要翻译：本发明涉及在平坦化或抛光过程中减少或完全防止Cu腐蚀。在本发明的一个方面中，RF信号用于在抛光之后在晶片表面前建立负偏压以消除Cu +或Cu 2+迁移。在本发明的另一方面，使用DC电压电源来建立负偏压。

4. 发明授权

US06376378B1 Polishing apparatus and method for forming an integrated circuit 失效
标题翻译：抛光装置和形成集成电路的方法
公开(公告)号：US06376378B1
公开(公告)日：2002-04-23
申请号：US09415364
申请日：1999-10-08
申请人： Feng Chen , Lup San Leong , Charles Lin
发明人： Feng Chen , Lup San Leong , Charles Lin
IPC分类号： H01L21461
CPC分类号： B24B37/042 , B24B37/20 , H01L21/31053 , H01L21/3212
摘要： In one embodiment, a dielectric layer (144, 156) overlying a semiconductor substrate (28) is uniformly polished. During polishing, the perimeter (32) of the semiconductor substrate (28) overlies a peripheral region (16, 48, 66, 86, 120) of a polishing pad (6, 42, 60, 80, 100) and an edge portion (36) of the front surface of semiconductor substrate (28) is not in contact with the front surface (18, 50, 68, 88, 122) of the polishing pad (6, 42, 60, 80, 100), in the peripheral region (16, 48, 66, 86, 120). As a result, the polishing rate at the edge portion (36) of the semiconductor substrate (28) is reduced, and the semiconductor substrate (28) is polished with improved center to edge uniformity. Since the semiconductor substrate (28) is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion (36) of the semiconductor substrate (28) are not over polished.
摘要翻译：在一个实施例中，覆盖半导体衬底（28）的电介质层（144,156）被均匀抛光。在抛光期间，半导体衬底（28）的周边（32）覆盖在抛光垫（6,42,60,80,100）和边缘部分（16,48,66,101）周边区域半导体衬底（28）的前表面的表面（36）不与抛光垫（6,42,60,80,100）的前表面（18,50,68,88,100）接触，区域（16,48,66,86,120）。结果，半导体衬底（28）的边缘部分（36）处的抛光速率降低，并且半导体衬底（28）以改善的中心到边缘均匀性被抛光。由于半导体基板（28）以改善的中心到边缘均匀性被抛光，所以由于位于半导体基板（28）的边缘部分（36）内的模具没有被过度抛光，所以提高了模具的产量。

5. 发明申请

US20140008810A1 METHOD FOR FORMING THROUGH SILICON VIA WITH WAFER BACKSIDE PROTECTION 有权
标题翻译：通过硅片防止背面保护形成硅的方法
公开(公告)号：US20140008810A1
公开(公告)日：2014-01-09
申请号：US13542256
申请日：2012-07-05
申请人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
发明人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
IPC分类号： H01L21/306 , H01L23/48
CPC分类号： H01L23/481 , H01L21/02107 , H01L21/486 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/13009 , H01L2224/1357
摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
摘要翻译：具有贯通硅通孔（TSV）的半导体器件不形成铜污染。实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层，硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到暴露TSV底部的触点。

6. 发明授权

US06730573B1 MIM and metal resistor formation at CU beol using only one extra mask 有权
标题翻译： MIM和金属电阻器形成在CU beol仅使用一个额外的掩模
公开(公告)号：US06730573B1
公开(公告)日：2004-05-04
申请号：US10286257
申请日：2002-11-01
申请人： Chit Hwei Ng , Chaw Sing Ho , Lup San Leong , Shao Kai , Raymond Jacob Joy , Sanford Chu , Sajan Marokkey Raphael
发明人： Chit Hwei Ng , Chaw Sing Ho , Lup San Leong , Shao Kai , Raymond Jacob Joy , Sanford Chu , Sajan Marokkey Raphael
IPC分类号： H01L2120
CPC分类号： H01L28/24 , H01L21/76838 , H01L23/5223 , H01L23/5228 , H01L23/5252 , H01L23/5329 , H01L27/0682 , H01L27/0805 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make
摘要翻译：已经开发了使用单镶嵌或双镶嵌加工制造同时高容量，小于0.13微米的金属 - 绝缘体 - 金属电容器，金属电阻器和金属互连的改进方法。关键的优点是同时使用一个额外的掩模掩模版同时形成MIM电容和电阻。克服了BEOL后端存在的几个当前的障碍，即：（a）使用两个或更多个光掩膜使<0.13μm的MIM电容器，（b）凹凸的铜表面，当电介质直接沉积时（c）当在底部MIM板层上尝试蚀刻停止时，（c）蚀刻期间的颗粒产生问题，最后，（d）在需要大的铜MIM板时发生CMP期间的凹陷，随后的电容匹配问题。该集成方法克服了上述障碍，同时使用镶嵌处理形成MIM电容器，金属电阻器和金属互连。此外，本文所述的形成MIM电容器的方法也可用于在现场可编程门阵列FPGA中形成反熔丝器件。

7. 发明授权

US08940637B2 Method for forming through silicon via with wafer backside protection 有权
标题翻译：通过硅晶片背面保护形成硅通孔的方法
公开(公告)号：US08940637B2
公开(公告)日：2015-01-27
申请号：US13542256
申请日：2012-07-05
申请人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
发明人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
IPC分类号： H01L21/44 , H01L21/768 , H01L21/48
CPC分类号： H01L23/481 , H01L21/02107 , H01L21/486 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/13009 , H01L2224/1357
摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
摘要翻译：具有贯通硅通孔（TSV）的半导体器件不形成铜污染。实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层，硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到暴露TSV底部的触点。

8. 发明授权

US08828858B2 Spacer profile engineering using films with continuously increased etch rate from inner to outer surface 有权
标题翻译：使用具有从内到外表面的不断增加的蚀刻速率的膜的间隔轮廓工程
公开(公告)号：US08828858B2
公开(公告)日：2014-09-09
申请号：US13353684
申请日：2012-01-19
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6653 , H01L29/6656
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
摘要翻译：通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

9. 发明申请

US20140117545A1 COPPER HILLOCK PREVENTION WITH HYDROGEN PLASMA TREATMENT IN A DEDICATED CHAMBER 审中-公开
标题翻译：铜矿床预防氢化等离子体处理
公开(公告)号：US20140117545A1
公开(公告)日：2014-05-01
申请号：US13661882
申请日：2012-10-26
申请人： Huang LIU , Xuesong Rao , Zheng Zou , Alex See , Lup San Leong , Liang Li , Chim Seng Seet
发明人： Huang LIU , Xuesong Rao , Zheng Zou , Alex See , Lup San Leong , Liang Li , Chim Seng Seet
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76883 , H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： A copper layer is formed without copper hillocks. Embodiments includes providing a copper layer above a substrate, planarizing the copper layer, performing hydrogen (H2) plasma treatment on the copper layer in a first chamber, and forming a barrier layer over the copper layer in a second chamber, different from the first chamber.
摘要翻译：形成铜层，没有铜质的小丘。实施例包括在基板上设置铜层，对铜层进行平坦化，对第一室中的铜层进行氢（H2）等离子体处理，以及在不同于第一室的第二室中的铜层上形成阻挡层。

10. 发明授权

US08492236B1 Step-like spacer profile 有权
标题翻译：阶梯状间隔剖面
公开(公告)号：US08492236B1
公开(公告)日：2013-07-23
申请号：US13348766
申请日：2012-01-12
申请人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
发明人： Xuesong Rao , Chim Seng Seet , Hai Cong , Zheng Zou , Alex See , Yun Ling Tan , Wen Zhan Zhou , Lup San Leong , Huang Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/78
摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
摘要翻译：通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物，像个人资料实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

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