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1. 发明申请

US20090315115A1 Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement 审中-公开
标题翻译：用于浅沟槽隔离（STI）形成和用于晶体管性能增强的应力的植入
公开(公告)号：US20090315115A1
公开(公告)日：2009-12-24
申请号：US12214854
申请日：2008-06-23
申请人： Beichao Zhang , Johnny Widodo , Juan Boon Tan , Yong Kong Siew , Fan Zhang , Haifeng Sheng , Wenhe Lin , Young Way Teh , Jinping Liu , Vincent Ho , Liang Choo Hsia
发明人： Beichao Zhang , Johnny Widodo , Juan Boon Tan , Yong Kong Siew , Fan Zhang , Haifeng Sheng , Wenhe Lin , Young Way Teh , Jinping Liu , Vincent Ho , Liang Choo Hsia
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823481 , H01L21/76224 , H01L29/7846
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.
摘要翻译：制造半导体器件的方法（和半导体器件）通过在STI区域中注入离子来提供浅沟槽隔离（STI）结构或区域。在植入之后，区域（衬底材料和不同元素的离子）进行热退火，产生用于隔离两个相邻的场效应晶体管（FET）的电介质材料。这消除了去除衬底材料以形成沟槽并用电介质材料重新填充沟槽的常规步骤。将氮离子注入到邻近p型FET的STI区域中，对晶体管沟道区域施加压缩应力以增强晶体管性能。将氧离子注入到与n型FET相邻的STI区域中，对晶体管沟道区域施加拉伸应力以增强晶体管性能。

2. 发明申请

US20050171423A1 WHOLE BODY MRI SCANNING WITH MOVING TABLE AND INTERACTIVE CONTROL 有权
标题翻译：全身MRI扫描与移动表和互动控制
公开(公告)号：US20050171423A1
公开(公告)日：2005-08-04
申请号：US10907883
申请日：2005-04-19
申请人： Vincent Ho , Thomas Foo
发明人： Vincent Ho , Thomas Foo
IPC分类号： G01R33/28 , A61B5/055 , G01R33/563 , G21K1/12 , H05G1/60 , A61B6/00 , G01N23/00 , A61B5/05
CPC分类号： G01R33/56375 , A61B5/0555 , G06F19/00
摘要： The present invention includes a method and apparatus for high sensitivity whole body scanning using MR imaging. The invention includes acquiring MR data as the patient moves through the iso-center of the magnet while providing interactive control for the operator to change scan parameters and table motion and direction. The technique allows efficient whole body scanning for fast screening of abnormalities while allowing operator control during the screening process to interrupt table motion and redirect the speed and direction of the table while also allowing control over the acquisition plane, number of sections imaged, inter-section spacing, and the scan location.
摘要翻译：本发明包括使用MR成像进行高灵敏度全身扫描的方法和装置。本发明包括当患者移动通过磁体的等中心时获取MR数据，同时为操作者提供交互式控制以改变扫描参数和表格运动和方向。该技术允许有效的全身扫描快速筛选异常，同时允许操作者在筛选过程中控制中断台面运动并重定向表的速度和方向，同时还允许控制采集平面，成像部分数量，间隔间距和扫描位置。

3. 发明授权

US08519445B2 Poly profile engineering to modulate spacer induced stress for device enhancement 有权
标题翻译：聚轮廓工程用于调制间隔物诱发的应力用于器件增强
公开(公告)号：US08519445B2
公开(公告)日：2013-08-27
申请号：US13182455
申请日：2011-07-14
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L27/10 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

4. 发明申请

US20100283101A1 PATTERNING NANOCRYSTAL LAYERS 有权
标题翻译：绘制纳米晶体层
公开(公告)号：US20100283101A1
公开(公告)日：2010-11-11
申请号：US12436793
申请日：2009-05-07
申请人： Yu CHEN , Jae Gon LEE , Vincent HO , Bangun INDAJANG
发明人： Yu CHEN , Jae Gon LEE , Vincent HO , Bangun INDAJANG
IPC分类号： H01L29/792 , H01L21/28 , H01L21/31
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11521 , H01L27/11526 , H01L27/11543 , H01L27/11568 , H01L27/11573 , H01L29/42348 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with first and second regions with a first device layer. A second device layer including nanocrystals is also formed. A cover layer is provided over the second device layer. The cover layer is patterned to expose portions of the second device layer in the first and second regions. The exposed portions of the second device layer in the first and second regions are processed to form modified portions. The processing of the exposed portions at least reduces the nanocrystals to a diameter below a threshold diameter in the modified portions. The modified portions are removed.
摘要翻译：提出了一种形成半导体器件的方法。该方法包括提供用第一和第二区域制备的具有第一器件层的衬底。还形成了包括纳米晶体的第二器件层。覆盖层设置在第二设备层上。将覆盖层图案化以暴露第一和第二区域中的第二器件层的部分。处理第一和第二区域中的第二装置层的暴露部分以形成修改部分。暴露部分的处理至少将纳米晶体的直径降低到修改部分中的阈值直径以下。去除改性部分。

5. 发明申请

US20100032847A1 METHOD FOR FORMING A PACKAGE-ON-PACKAGE STRUCTURE 失效
标题翻译：用于形成包装封装结构的方法
公开(公告)号：US20100032847A1
公开(公告)日：2010-02-11
申请号：US12188866
申请日：2008-08-08
申请人： Asri bin Yusof , Vincent Ho
发明人： Asri bin Yusof , Vincent Ho
IPC分类号： H01L21/50 , H01L23/00
CPC分类号： H01L23/49816 , H01L21/67092 , H01L21/6835 , H01L23/13 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/105 , H01L25/50 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for forming a package-on-package structure is disclosed. The method comprises the step of providing a first semiconductor package. The first semiconductor package has at least one encapsulation layer formed on at least one side of the first semiconductor package. The method also involves the step of securing the first semiconductor package to a surface. The surface is adapted for receiving the first semiconductor package. The method further involves the step of reducing the thickness of the at least one encapsulation layer to a predetermined thickness. The at least one encapsulation layer having a portion distal the surface removed. More specifically, the thickness of the at least one encapsulation layer is reduced for providing a predetermined clearance from a second semiconductor package attachable to the first semiconductor package. The clearance is the distance between the at least one encapsulation layer of the first semiconductor package and a side of the second semiconductor package opposing thereto.
摘要翻译：公开了一种用于形成封装封装结构的方法。该方法包括提供第一半导体封装的步骤。第一半导体封装具有形成在第一半导体封装的至少一侧上的至少一个封装层。该方法还包括将第一半导体封装固定到表面的步骤。表面适于接收第一半导体封装。该方法还包括将至少一个封装层的厚度减小到预定厚度的步骤。所述至少一个封装层具有远离所述表面的部分去除。更具体地，减小了至少一个封装层的厚度，以便从可附接到第一半导体封装的第二半导体封装提供预定间隙。间隙是第一半导体封装的至少一个封装层和与其相对的第二半导体封装的一侧之间的距离。

6. 发明申请

US20050078882A1 Pixelation reconstruction for image resolution and image data transmission 有权
标题翻译：图像分辨率和图像数据传输的像素重建
公开(公告)号：US20050078882A1
公开(公告)日：2005-04-14
申请号：US10686194
申请日：2003-10-09
申请人： Vincent Ho , Micah Schmidt
发明人： Vincent Ho , Micah Schmidt
IPC分类号： G06K9/32 , G06K9/40 , G06T3/40 , G06T5/00
CPC分类号： G06T3/40 , G06T5/003 , G06T5/10 , G06T2207/10088 , G06T2207/20056 , G06T2207/30004
摘要： Methods for improving spatial and/or temporal resolution of digital images and for improving image data transmission by a novel technique—back pixelation, which involves data processing and reconstruction of overlaid images from multiple acquisition or multiple sampling. The back pixelation technique may be used for image data acquisition and transmission; it may be applied prospectively or retrospectively. In particular, the methods of this invention may be used in reducing the pixel size of a two-dimensional image or the voxel size of a three dimensional image; producing a two- or three-dimensional image from a multiplicity of images acquired from an object which are capable of overlaying one another by an increment; producing and transmitting a two- or three-dimensional image by multiple acquisitions according to an acquisition matrix; or transmitting a two- or three-dimensional image by reducing or decomposing the image to a plurality of image data packets and transmitting the same. The multiple acquisitions may be arranged by a predetermined temporal schedule. These methods may be advantageously applied in medical imaging, movies and video games, teleimage, and any other areas that involve digital image acquisition, processing, and transmission.
摘要翻译：用于改进数字图像的空间和/或时间分辨率以及通过新技术回扫像素化来改进图像数据传输的方法，其涉及从多次采集或多次采样中重叠图像的数据处理和重建。后像素化技术可用于图像数据采集和传输; 可以应用于前瞻性或追溯性。特别地，本发明的方法可用于减小二维图像的像素大小或三维图像的体素大小; 从能够通过增量彼此叠加的从对象获取的多个图像产生二维或三维图像; 根据采集矩阵通过多次采集产生和发送二维或三维图像; 或者通过将图像减少或分解为多个图像数据分组并发送图像数据分组来发送二维或三维图像。多个采集可以按照预定的时间表进行排列。这些方法可以有利地应用于医学成像，电影和视频游戏，电传图像以及涉及数字图像采集，处理和传输的任何其它领域。

7. 发明申请

US20110266628A1 POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT 有权
标题翻译： POLY PROFILE工程来调节间隔器感应应变的设备增强
公开(公告)号：US20110266628A1
公开(公告)日：2011-11-03
申请号：US13182455
申请日：2011-07-14
申请人： Vincent HO , Wenhe LIN , Young Way TEH , Yong Kong SIEW , Bei Chao ZHANG , Fan ZHANG , Haifeng SHENG , Juan Boon TAN
发明人： Vincent HO , Wenhe LIN , Young Way TEH , Yong Kong SIEW , Bei Chao ZHANG , Fan ZHANG , Haifeng SHENG , Juan Boon TAN
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

8. 发明授权

US07993997B2 Poly profile engineering to modulate spacer induced stress for device enhancement 有权
标题翻译：聚轮廓工程用于调制间隔物诱发的应力用于器件增强
公开(公告)号：US07993997B2
公开(公告)日：2011-08-09
申请号：US11865563
申请日：2007-10-01
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

9. 发明授权

US07901988B2 Method for forming a package-on-package structure 失效
标题翻译：用于形成封装在封装结构上的方法
公开(公告)号：US07901988B2
公开(公告)日：2011-03-08
申请号：US12188866
申请日：2008-08-08
申请人： Asri bin Yusof , Vincent Ho
发明人： Asri bin Yusof , Vincent Ho
IPC分类号： H01L21/44
CPC分类号： H01L23/49816 , H01L21/67092 , H01L21/6835 , H01L23/13 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/105 , H01L25/50 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for forming a package-on-package structure is disclosed. The method comprises the step of providing a first semiconductor package. The first semiconductor package has at least one encapsulation layer formed on at least one side of the first semiconductor package. The method also involves the step of securing the first semiconductor package to a surface. The surface is adapted for receiving the first semiconductor package. The method further involves the step of reducing the thickness of the at least one encapsulation layer to a predetermined thickness. The at least one encapsulation layer having a portion distal the surface removed. More specifically, the thickness of the at least one encapsulation layer is reduced for providing a predetermined clearance from a second semiconductor package attachable to the first semiconductor package. The clearance is the distance between the at least one encapsulation layer of the first semiconductor package and a side of the second semiconductor package opposing thereto.
摘要翻译：公开了一种用于形成封装封装结构的方法。该方法包括提供第一半导体封装的步骤。第一半导体封装具有形成在第一半导体封装的至少一侧上的至少一个封装层。该方法还包括将第一半导体封装固定到表面的步骤。表面适于接收第一半导体封装。该方法还包括将至少一个封装层的厚度减小到预定厚度的步骤。所述至少一个封装层具有远离所述表面的部分去除。更具体地，减小了至少一个封装层的厚度，以便从可附接到第一半导体封装的第二半导体封装提供预定间隙。间隙是第一半导体封装的至少一个封装层和与其相对的第二半导体封装的一侧之间的距离。

10. 发明申请

US20090085122A1 POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT 有权
标题翻译： POLY PROFILE工程来调节间隔器感应应变的设备增强
公开(公告)号：US20090085122A1
公开(公告)日：2009-04-02
申请号：US11865563
申请日：2007-10-01
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

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