专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08618870B2 Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit 失效
标题翻译：锁存电路的电压特性调节方法，半导体器件的电压特性调节方法和锁存电路的电压特性调节器
公开(公告)号：US08618870B2
公开(公告)日：2013-12-31
申请号：US13377009
申请日：2010-06-11
申请人： Toshiro Hiramoto , Takayasu Sakurai , Makoto Suzuki
发明人： Toshiro Hiramoto , Takayasu Sakurai , Makoto Suzuki
IPC分类号： G05F1/10
CPC分类号： G11C11/413
摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.
摘要翻译：电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对导通晶体管的栅极与半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善。

2. 发明申请

US20120182064A1 VOLTAGE CHARACTERISTIC REGULATING METHOD OF LATCH CIRCUIT, VOLTAGE CHARACTERISTIC REGULATING METHOD OF SEMICONDUCTOR DEVICE, AND VOLTAGE CHARACTERISTIC REGULATOR OF LATCH CIRCUIT 失效
标题翻译：电压电路的特性调节方法，半导体器件的电压特性调节方法和电压电路特性调节器
公开(公告)号：US20120182064A1
公开(公告)日：2012-07-19
申请号：US13377009
申请日：2010-06-11
申请人： Toshiro Hiramoto , Takayasu Sakurai , Makoto Suzuki
发明人： Toshiro Hiramoto , Takayasu Sakurai , Makoto Suzuki
IPC分类号： G05F1/10
CPC分类号： G11C11/413
摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.
摘要翻译：电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对导通晶体管的栅极和半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善。

3. 发明授权

US06529042B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06529042B1
公开(公告)日：2003-03-04
申请号：US09548658
申请日：2000-04-13
申请人： Toshiro Hiramoto , Takayasu Sakurai , Takashi Inukai
发明人： Toshiro Hiramoto , Takayasu Sakurai , Takashi Inukai
IPC分类号： H03K19094
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit of the present invention has a CMOS circuit 1 composed of a first MOSFET and a switch 2 composed of a second MOSFET which are connected in series. Then, a circuit-driving voltage and a switch-driving voltage are applied independently to the CMOS circuit 1 and the switch 2. The switch-driving voltage is larger than the circuit-driving voltage.
摘要翻译：本发明的半导体集成电路具有由第一MOSFET和由串联连接的第二MOSFET构成的开关2构成的CMOS电路1。然后，电路驱动电压和开关驱动电压独立地施加到CMOS电路1和开关2.开关驱动电压大于电路驱动电压。

4. 发明授权

US5457412A Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals 失效
标题翻译：半导体集成电路器件包括输入电路，以允许具有ECL电平输入信号的Bi-CMOS存储器的操作
公开(公告)号：US5457412A
公开(公告)日：1995-10-10
申请号：US149935
申请日：1993-11-10
申请人： Nobuo Tamba , Masanori Odaka , Toshiro Hiramoto , Masayuki Ohayashi , Kayoko Saito
发明人： Nobuo Tamba , Masanori Odaka , Toshiro Hiramoto , Masayuki Ohayashi , Kayoko Saito
IPC分类号： G11C11/413 , H01L21/8249 , H01L27/06 , H03K19/0175 , H03K19/08
CPC分类号： H03K19/017527
摘要： A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.
摘要翻译：提供了一种半导体集成电路器件，用于允许具有ECL电平输入信号的CMOS或BiCMOS存储器的操作，其中操作速度增加并且功耗降低。 ECL电平的输入信号由输入缓冲器接收，用于将输入信号放大到输入缓冲器的差分晶体管在不饱和区域中操作的范围内的输出信号电平。输入缓冲器的输出信号被提供给CMOS电路或Bi-CMOS电路，该CMOS电路或Bi-CMOS电路由具有比输入缓冲器的工作电压的绝对值小的第一级的工作电压和电路。该第一级CMOS或BiCMOS电路还包括进一步放大接收信号以提供进一步电平转换的装置。由于输入缓冲器和第一级CMOS或Bi-CMOS电路都执行信号传输和电平转换，所以可以通过简单的结构实现高速操作和低功耗。

5. 发明授权

US5255225A Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit 失效
标题翻译：半导体集成电路器件和存储器由半导体集成电路组成
公开(公告)号：US5255225A
公开(公告)日：1993-10-19
申请号：US845557
申请日：1992-03-04
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
IPC分类号： G11C5/14 , G11C7/10 , G11C11/40
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.The speed of an operation of the circuit device can be increased to a high level owing to a simple circuit in which a level, which is required to attain an output amplitude, of complementary output signals is secured by the current switch circuit, the amplified complementary signals being inputted into the emitter follower circuit to directly drive the output transistor.
摘要翻译：提供一种包括电平转换电路的半导体集成电路器件，其中电路的简化和操作速度的提高已经达到。通过包括接收输入信号和参考电压的差分晶体管的电流开关电路将被放大到所需信号电平的一对互补输出信号输入到一对发射极跟随器电路中。射极跟随器输出晶体管由来自一个射极跟随器电路的输出信号驱动，而在输出晶体管和用作负载的电流源之间提供的N沟道MOSFET由另一个射极跟随器电路的输出信号驱动到从输出晶体管的发射极获得电平放大的输出信号。电路装置的运行速度可以通过电流开关电路确保互补输出信号的达到输出幅度所需的电平的简单电路而增加到高电平，放大的互补信号被输入射极跟随器电路以直接驱动输出晶体管。

6. 发明授权

US06989569B1 MOS transistor with a controlled threshold voltage 失效
标题翻译：具有受控阈值电压的MOS晶体管
公开(公告)号：US06989569B1
公开(公告)日：2006-01-24
申请号：US09389321
申请日：1999-09-03
申请人： Toshiro Hiramoto , Makoto Takamiya
发明人： Toshiro Hiramoto , Makoto Takamiya
IPC分类号： H01L29/78
CPC分类号： H01L29/78609 , H01L29/783 , H01L29/78648
摘要： A MOS transistor with a controlled threshold voltage includes a SOI which includes a substrate composed of a semi-conducting material, a single crystal layer composed of a semi-conducting material and an insulating layer interposed between the substrate and the single crystal layer. The single crystal layer is formed therein with a source region, a drain region and a surrounded region surrounded by the source region and the drain region. The surrounded region includes a depletion layer having a composition surface which is in contact with the insulating layer. The MOS transistor comprises an EIB-MOS transistor of which the substrate is adapted to be applied with a voltage of a first polarity for inducing charges of a second polarity over the composition surface of the surrounded region.
摘要翻译：具有受控阈值电压的MOS晶体管包括SOI，其包括由半导体材料构成的衬底，由半导体材料构成的单晶层和插入在衬底和单晶层之间的绝缘层。单晶层在其中形成有源极区域，漏极区域和由源极区域和漏极区域包围的被包围的区域。被包围的区域包括具有与绝缘层接触的组成表面的耗尽层。 MOS晶体管包括EIB-MOS晶体管，其基板适于施加第一极性的电压，用于在所包围的区域的组成表面上诱导第二极性的电荷。

7. 发明授权

US5661329A Semiconductor integrated circuit device including an improved separating groove arrangement 失效
标题翻译：半导体集成电路器件包括改进的分离槽布置
公开(公告)号：US5661329A
公开(公告)日：1997-08-26
申请号：US350944
申请日：1994-12-07
申请人： Toshiro Hiramoto , Nobuo Tamba , Masami Usami , Takahide Ikeda , Kazuo Tanaka , Atsuo Watanabe , Satoru Isomura , Toshiyuki Kikuchi , Toru Koizumi
发明人： Toshiro Hiramoto , Nobuo Tamba , Masami Usami , Takahide Ikeda , Kazuo Tanaka , Atsuo Watanabe , Satoru Isomura , Toshiyuki Kikuchi , Toru Koizumi
IPC分类号： H01L21/84 , H01L27/12 , H01L29/10 , H01L29/00 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/1079
摘要： A semiconductor integrated circuit device includes an element separating first and second grooves formed to surround active regions to be formed with a semiconductor element. In addition a third groove is formed to surround at least a portion of the first groove, when viewed from a plane view. In the semiconductor integrated circuit device, the active regions and an element separating region of a silicon layer are insulated from each other by the separating grooves extending from the main surface of the silicon layer to an underlying insulating layer, and are fed with a common fixed potential.
摘要翻译：半导体集成电路器件包括分离形成为围绕要形成半导体元件的有源区的第一和第二沟槽的元件。此外，当从平面视图观察时，形成第三凹槽以围绕第一凹槽的至少一部分。在半导体集成电路器件中，硅层的有源区域和元件分离区域通过从硅层的主表面延伸到下面的绝缘层的分离槽彼此绝缘，并且被馈送有公共固定潜在。

8. 发明授权

US5519658A Semiconductor integrated circuit device and methods for production thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5519658A
公开(公告)日：1996-05-21
申请号：US332078
申请日：1994-11-01
申请人： Takayuki Uda , Toshiro Hiramoto , Nobuo Tamba , Hisashi Ishida , Kazuhiro Akimoto , Masanori Odaka , Tasuku Tanaka , Jun Hirokawa , Masayuki Ohayashi
发明人： Takayuki Uda , Toshiro Hiramoto , Nobuo Tamba , Hisashi Ishida , Kazuhiro Akimoto , Masanori Odaka , Tasuku Tanaka , Jun Hirokawa , Masayuki Ohayashi
IPC分类号： H01L21/60 , H01L23/055 , H01L23/525 , H01L27/118 , G11C7/00
CPC分类号： H01L24/81 , H01L23/055 , H01L23/5256 , H01L24/11 , H01L27/118 , H01L2224/0401 , H01L2224/05567 , H01L2224/05572 , H01L2224/1147 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/73253 , H01L2224/81801 , H01L23/3171 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/0107 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/19043 , H01L2924/3011 , H01L2924/3025
摘要： Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage. This allows a faulty circuit to be replaced with the corresponding redundancy circuit.
摘要翻译：公开了半导体集成电路装置及其制造方法。本发明的实施例是一种半导体芯片，其包括构成其中形成的冗余电路的一部分的保险丝，该保险丝由相同成分CCB凸块基底金属制成。在CCB凸块基板金属的图案化期间，熔丝同时被图案化。这涉及使用芯片中的电极导体图案的成分的至少一部分来形成保险丝。保险丝的切割区域仅由构成基板的金属层中的一个构成。半导体芯片的主平面具有至少形成在保险丝的切割区域上的保险丝保护膜，用于保护保险丝。在操作中，使用冗余信号的开关控制下的开关MOSFET来选择两个传输路径中的一个，一个传送地址信号或解码信号，另一个传送参考电压。这样可以将故障电路替换为相应的冗余电路。

9. 发明授权

US5854497A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5854497A
公开(公告)日：1998-12-29
申请号：US773312
申请日：1996-12-24
申请人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
发明人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , H01L29/76 , G11C11/00
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.
摘要翻译：一种半导体存储器件，具有多个存储单元，每个存储单元包括彼此交叉耦合并且布置在沿列方向延伸的多个字线和沿行方向延伸的多个互补数据线对的交点处的两个CMOS反相器; 其中沿着列方向布置的存储单元的p沟道型负载MISFET形成在n型阱区域的字线延伸方向的主表面上，p沟道型负载MISFET的源极区域沿列方向布置的存储单元通过导体层电连接到n型阱区，并且每个导体层独立于沿列方向排列的存储单元而形成。更具体地，n型阱区域被馈送有第一固定电位，并且每个p沟道型负载MISFET的源极区域通过独立形成的导体层馈送第一固定电位。

10. 发明授权

US5594270A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5594270A
公开(公告)日：1997-01-14
申请号：US314775
申请日：1994-09-29
申请人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
发明人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , H01L29/76 , G11C11/00
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction. More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.
摘要翻译：一种半导体存储器件，具有多个存储单元，每个存储单元包括彼此交叉耦合并且布置在沿列方向延伸的多个字线和沿行方向延伸的多个互补数据线对的交点处的两个CMOS反相器; 其中沿着列方向布置的存储单元的p沟道型负载MISFET形成在n型阱区域的字线延伸方向的主表面上，p沟道型负载MISFET的源极区域沿列方向布置的存储单元通过导体层电连接到n型阱区，并且每个导体层独立于沿列方向排列的存储单元而形成。更具体地，n型阱区域被馈送有第一固定电位，并且每个p沟道型负载MISFET的源极区域通过独立形成的导体层馈送第一固定电位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式