专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07238582B2 Semiconductor device and process of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07238582B2
公开(公告)日：2007-07-03
申请号：US11000092
申请日：2004-12-01
申请人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
发明人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01L21/8222
CPC分类号： H01L27/0652 , H01L27/0688 , H01L28/20
摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
摘要翻译：本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二多晶硅层具有负电阻的温度依赖性，反之亦然。此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

2. 发明授权

US06208010B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06208010B1
公开(公告)日：2001-03-27
申请号：US08574110
申请日：1995-12-18
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L2900
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0218 , H01L27/0623 , H01L27/0922 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

3. 发明授权

US5726488A Semiconductor device having semiconductor elements formed in a retrograde well structure 失效
标题翻译：具有形成在逆行井结构中的半导体元件的半导体器件
公开(公告)号：US5726488A
公开(公告)日：1998-03-10
申请号：US243325
申请日：1994-05-16
申请人： Atsuo Watanabe , Yoshiaki Yazawa , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano , Takahide Ikeda , Naohiro Momma
发明人： Atsuo Watanabe , Yoshiaki Yazawa , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano , Takahide Ikeda , Naohiro Momma
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78 , H01L27/02
CPC分类号： H01L27/0623 , H01L21/8238 , H01L21/8249 , Y10S257/921
摘要： A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
摘要翻译：半导体器件具有在衬底的表面中形成的阱区，并且具有形成在阱区中的诸如MOSFET和双极晶体管的功能部分。阱区域的载流子浓度分布呈深谷方向的谷状，其最小点浓度小于5×10 15 cm -3，位于距离其表面1.6m以内的位置底物。优选地，最小点应该具有大于5×10 14 cm -3但小于5×10 15 cm -3的浓度，更优选大于1×10 15 cm -3但小于5×10 15 cm -3的浓度。

4. 发明授权

US5619069A Bipolar device and production thereof 失效
标题翻译：双极器件及其生产
公开(公告)号：US5619069A
公开(公告)日：1997-04-08
申请号：US458655
申请日：1995-06-02
申请人： Hiroyuki Ohta , Hideo Miura , Hiroo Masuda , Yoichi Tamaki , Takahide Ikeda , Asao Nishimura , Takashi Hashimoto
发明人： Hiroyuki Ohta , Hideo Miura , Hiroo Masuda , Yoichi Tamaki , Takahide Ikeda , Asao Nishimura , Takashi Hashimoto
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L23/485 , H01L27/06 , H01L29/732 , H01L23/48
CPC分类号： H01L23/4855 , H01L23/485 , H01L2924/0002 , Y10S148/01 , Y10S148/124 , Y10S148/135
摘要： A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.
摘要翻译：具有硅基板中的基极的接触面积电平与基极区域之间的电平差的硅双极器件，以及硅基板的发射电极和发射极区域的接触面积电平为0.03μm〜通过从发射极区域去除不需要的杂质并且侧壁和器件隔离膜之间的预定水平距离不产生位错并且显示出良好的电特性，0.1μm。

5. 发明授权

US5354699A Method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5354699A
公开(公告)日：1994-10-11
申请号：US964824
申请日：1992-10-22
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265
CPC分类号： H01L21/28026 , H01L21/28525 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

6. 发明授权

US5049967A Semiconductor integrated circuit device and a method for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5049967A
公开(公告)日：1991-09-17
申请号：US631907
申请日：1990-12-21
申请人： Atsuo Watanabe , Takahide Ikeda , Kiyoshi Tsukuda , Mitsuru Hirao , Touji Mukai , Tatsuya Kamei
发明人： Atsuo Watanabe , Takahide Ikeda , Kiyoshi Tsukuda , Mitsuru Hirao , Touji Mukai , Tatsuya Kamei
IPC分类号： H01L27/08 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/68 , H01L29/78
CPC分类号： H01L27/11896 , H01L21/8249 , H01L27/0623
摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from a surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

7. 发明申请

US20050101097A1 Semiconductor device and process of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050101097A1
公开(公告)日：2005-05-12
申请号：US11000092
申请日：2004-12-01
申请人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
发明人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01C7/06 , H01L21/02 , H01L21/822 , H01L27/04 , H01L27/06 , H01L21/20 , H01L21/8222
CPC分类号： H01L27/0652 , H01L27/0688 , H01L28/20
摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
摘要翻译：本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二多晶硅层具有负电阻的温度依赖性，反之亦然。此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

8. 发明授权

US6133094A Semiconductor device and process of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US6133094A
公开(公告)日：2000-10-17
申请号：US123405
申请日：1998-07-28
申请人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
发明人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01C7/06 , H01L21/02 , H01L21/822 , H01L27/04 , H01L27/06 , H01L21/336
CPC分类号： H01L27/0652 , H01L27/0688 , H01L28/20
摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
摘要翻译：本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二多晶层具有负电阻的温度依赖性，反之亦然。此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

9. 发明授权

US5512497A Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US5512497A
公开(公告)日：1996-04-30
申请号：US272312
申请日：1994-07-08
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265 , H01L21/8238
CPC分类号： H01L21/28026 , H01L21/28525 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

10. 发明授权

US5508549A Semiconductor integrated circuit device and a method for manufacturing the same 失效
公开(公告)号：US5508549A
公开(公告)日：1996-04-16
申请号：US735948
申请日：1991-07-25
申请人： Atsuo Watanabe , Takahide Ikeda , Kiyoshi Tsukuda , Mitsuru Hirao , Touji Mukai , Tatsuya Kamei
发明人： Atsuo Watanabe , Takahide Ikeda , Kiyoshi Tsukuda , Mitsuru Hirao , Touji Mukai , Tatsuya Kamei
IPC分类号： H01L27/08 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/68 , H01L29/78 , H01L27/02
CPC分类号： H01L27/11896 , H01L21/8249 , H01L27/0623
摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式