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1. 发明授权

US5825203A Variable logic integrated circuit device having connections through switch matrix and top layers for inter-cell connections 失效
标题翻译：可变逻辑集成电路器件具有通过开关矩阵和顶层连接的单元间连接的连接
公开(公告)号：US5825203A
公开(公告)日：1998-10-20
申请号：US747339
申请日：1996-11-12
申请人： Mitsugu Kusunoki , Nobuo Tamba
发明人： Mitsugu Kusunoki , Nobuo Tamba
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17792
摘要： A variable logic integrated circuit device formed on a semiconductor chip comprising variable logic blocks and switch matrices laid out alternately in the X and Y directions in a checkerboard pattern. Above the variable logic blocks is a block interconnection wiring arrangement formed by multiple-layer wiring techniques. The variable logic blocks and switch matrices are wired into circuits respectively by a lower wiring layer in the multiple wiring layer setup of the chip. The block interconnection wiring is formed by an upper wiring layer extending above the variable logic blocks and included in the multiple wiring layer setup. The switch matrices are used to connect the block interconnection lines to one another as well as to the variable logic blocks.
摘要翻译：形成在半导体芯片上的可变逻辑集成电路器件，其包括以棋盘图案在X和Y方向交替布置的可变逻辑块和开关矩阵。可变逻辑块之上是通过多层布线技术形成的块互连布线布置。可变逻辑块和开关矩阵分别通过芯片的多个布线层设置中的下布线层布线到电路中。块互连布线由在可变逻辑块之上延伸并包括在多个布线层设置中的上布线层形成。开关矩阵用于将块互连线彼此连接到可变逻辑块。

2. 发明授权

US5512497A Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US5512497A
公开(公告)日：1996-04-30
申请号：US272312
申请日：1994-07-08
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265 , H01L21/8238
CPC分类号： H01L21/28026 , H01L21/28525 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

3. 发明授权

US4903093A Semiconductor integrated circuit device double isolated CMOS input protection resistor 失效
标题翻译：半导体集成电路器件双隔离CMOS输入保护电阻
公开(公告)号：US4903093A
公开(公告)日：1990-02-20
申请号：US199671
申请日：1988-05-27
申请人： Akira Ide , Koichi Motohashi , Masanori Odaka , Nobuo Tamba
发明人： Akira Ide , Koichi Motohashi , Masanori Odaka , Nobuo Tamba
IPC分类号： H01L21/8249 , H01L21/331 , H01L27/02 , H01L27/06 , H01L27/10 , H01L27/105 , H01L29/73 , H01L29/732
CPC分类号： H01L27/0288 , H01L27/0251 , H01L27/105
摘要： In a semiconductor integrated circuit device, input protective elements have current limiting resistors which are diffused resistors of a second conductivity type formed in a first semiconductor region of a first conductivity type isolated electrically by a second semiconductor region of the second conductivity type, with the first conductivity type semiconductor region being in a floating state electrically. The input protective elements create less leak current and have high electrostatic durability.
摘要翻译：在半导体集成电路器件中，输入保护元件具有限流电阻，其是第二导电类型的扩散电阻器，形成在由第二导电类型的第二半导体区域电隔离的第一导电类型的第一半导体区域中，导电型半导体区域处于浮置状态。输入保护元件产生更少的漏电流并具有高静电耐久性。

4. 发明授权

US5852365A Variable logic circuit and semiconductor integrated circuit using the same 失效
标题翻译：可变逻辑电路和半导体集成电路使用相同
公开(公告)号：US5852365A
公开(公告)日：1998-12-22
申请号：US712554
申请日：1996-09-13
申请人： Nobuo Tamba , Mitsugu Kusunoki , Takeshi Miyazaki , Akira Masaki , Akira Yamagiwa
发明人： Nobuo Tamba , Mitsugu Kusunoki , Takeshi Miyazaki , Akira Masaki , Akira Yamagiwa
IPC分类号： H03K19/177 , H03K19/173 , H03K19/082 , H03K7/38
CPC分类号： H03K19/1737
摘要： A variable logic circuit comprises a memory cell, a transistor which turns on or off depending on data stored in the memory cell, a transistor which is connected in series to the above-mentioned transistor and is turned on or off by an input signal, a transistor which produces a voltage depending on the conduction states of the above-mentioned transistors, and transfer means which conducts or does not conduct the produced voltage to the output terminal depending on a select signal.
摘要翻译：可变逻辑电路包括存储单元，根据存储在存储单元中的数据导通或截止的晶体管，与上述晶体管串联连接并通过输入信号导通或截止的晶体管，晶体管，其根据上述晶体管的导通状态产生电压，以及根据选择信号将导通或不导通所产生的电压的输出装置输出到输出端。

5. 发明授权

US5661329A Semiconductor integrated circuit device including an improved separating groove arrangement 失效
标题翻译：半导体集成电路器件包括改进的分离槽布置
公开(公告)号：US5661329A
公开(公告)日：1997-08-26
申请号：US350944
申请日：1994-12-07
申请人： Toshiro Hiramoto , Nobuo Tamba , Masami Usami , Takahide Ikeda , Kazuo Tanaka , Atsuo Watanabe , Satoru Isomura , Toshiyuki Kikuchi , Toru Koizumi
发明人： Toshiro Hiramoto , Nobuo Tamba , Masami Usami , Takahide Ikeda , Kazuo Tanaka , Atsuo Watanabe , Satoru Isomura , Toshiyuki Kikuchi , Toru Koizumi
IPC分类号： H01L21/84 , H01L27/12 , H01L29/10 , H01L29/00 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/1079
摘要： A semiconductor integrated circuit device includes an element separating first and second grooves formed to surround active regions to be formed with a semiconductor element. In addition a third groove is formed to surround at least a portion of the first groove, when viewed from a plane view. In the semiconductor integrated circuit device, the active regions and an element separating region of a silicon layer are insulated from each other by the separating grooves extending from the main surface of the silicon layer to an underlying insulating layer, and are fed with a common fixed potential.
摘要翻译：半导体集成电路器件包括分离形成为围绕要形成半导体元件的有源区的第一和第二沟槽的元件。此外，当从平面视图观察时，形成第三凹槽以围绕第一凹槽的至少一部分。在半导体集成电路器件中，硅层的有源区域和元件分离区域通过从硅层的主表面延伸到下面的绝缘层的分离槽彼此绝缘，并且被馈送有公共固定潜在。

6. 发明授权

US5610535A Programmable two-line, two-phase logic array 失效
标题翻译：可编程双线，两相逻辑阵列
公开(公告)号：US5610535A
公开(公告)日：1997-03-11
申请号：US533990
申请日：1995-09-27
申请人： Akira Masaki , Makoto Kuwata , Ryuichi Satomura , Nobuo Tamba
发明人： Akira Masaki , Makoto Kuwata , Ryuichi Satomura , Nobuo Tamba
IPC分类号： G06F7/00 , H01L21/82 , H03K19/173 , H03K19/177 , H03K19/94 , H03K7/38
CPC分类号： H03K19/17704
摘要： A programmable two-line, two-phase logic array has a plurality of inputs, each having two input signals operating in two phases and memory cells provided at an intersection of the input signal lines and output lines corresponding to at least one function that cross the input lines. The memory cells are capable of being written in the fabrication process or by a field programming process that addresses the contact points at which the input and output lines cross. The two-line, two-phase logic circuit can be attained by the same technique as that used for attaining a conventional PLA without designing circuitry based on a conventional synchronous logic beforehand followed by replacing it with a two-line, two-phase circuit.
摘要翻译：可编程的双线两相逻辑阵列具有多个输入，每个输入具有在两相中工作的两个输入信号，并且提供在与输入信号线和输出线相对应的至少一个功能的交点处的存储单元输入线。存储器单元能够被写入制造过程中或通过现场编程处理来处理输入和输出线交叉的接触点。双线两相逻辑电路可以通过与用于实现常规PLA相同的技术获得，而不需要预先设计基于常规同步逻辑的电路，然后用双线两相电路替换它。

7. 发明授权

US5519658A Semiconductor integrated circuit device and methods for production thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5519658A
公开(公告)日：1996-05-21
申请号：US332078
申请日：1994-11-01
申请人： Takayuki Uda , Toshiro Hiramoto , Nobuo Tamba , Hisashi Ishida , Kazuhiro Akimoto , Masanori Odaka , Tasuku Tanaka , Jun Hirokawa , Masayuki Ohayashi
发明人： Takayuki Uda , Toshiro Hiramoto , Nobuo Tamba , Hisashi Ishida , Kazuhiro Akimoto , Masanori Odaka , Tasuku Tanaka , Jun Hirokawa , Masayuki Ohayashi
IPC分类号： H01L21/60 , H01L23/055 , H01L23/525 , H01L27/118 , G11C7/00
CPC分类号： H01L24/81 , H01L23/055 , H01L23/5256 , H01L24/11 , H01L27/118 , H01L2224/0401 , H01L2224/05567 , H01L2224/05572 , H01L2224/1147 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/73253 , H01L2224/81801 , H01L23/3171 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/0107 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/19043 , H01L2924/3011 , H01L2924/3025
摘要： Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage. This allows a faulty circuit to be replaced with the corresponding redundancy circuit.
摘要翻译：公开了半导体集成电路装置及其制造方法。本发明的实施例是一种半导体芯片，其包括构成其中形成的冗余电路的一部分的保险丝，该保险丝由相同成分CCB凸块基底金属制成。在CCB凸块基板金属的图案化期间，熔丝同时被图案化。这涉及使用芯片中的电极导体图案的成分的至少一部分来形成保险丝。保险丝的切割区域仅由构成基板的金属层中的一个构成。半导体芯片的主平面具有至少形成在保险丝的切割区域上的保险丝保护膜，用于保护保险丝。在操作中，使用冗余信号的开关控制下的开关MOSFET来选择两个传输路径中的一个，一个传送地址信号或解码信号，另一个传送参考电压。这样可以将故障电路替换为相应的冗余电路。

8. 发明授权

US5057894A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5057894A
公开(公告)日：1991-10-15
申请号：US526696
申请日：1990-05-23
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/285 , H01L21/8249 , H01L27/06
CPC分类号： H01L27/0623 , H01L21/28525 , H01L21/8249
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

9. 发明授权

US5854497A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5854497A
公开(公告)日：1998-12-29
申请号：US773312
申请日：1996-12-24
申请人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
发明人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , H01L29/76 , G11C11/00
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.
摘要翻译：一种半导体存储器件，具有多个存储单元，每个存储单元包括彼此交叉耦合并且布置在沿列方向延伸的多个字线和沿行方向延伸的多个互补数据线对的交点处的两个CMOS反相器; 其中沿着列方向布置的存储单元的p沟道型负载MISFET形成在n型阱区域的字线延伸方向的主表面上，p沟道型负载MISFET的源极区域沿列方向布置的存储单元通过导体层电连接到n型阱区，并且每个导体层独立于沿列方向排列的存储单元而形成。更具体地，n型阱区域被馈送有第一固定电位，并且每个p沟道型负载MISFET的源极区域通过独立形成的导体层馈送第一固定电位。

10. 发明授权

US5594270A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5594270A
公开(公告)日：1997-01-14
申请号：US314775
申请日：1994-09-29
申请人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
发明人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , H01L29/76 , G11C11/00
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction. More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.
摘要翻译：一种半导体存储器件，具有多个存储单元，每个存储单元包括彼此交叉耦合并且布置在沿列方向延伸的多个字线和沿行方向延伸的多个互补数据线对的交点处的两个CMOS反相器; 其中沿着列方向布置的存储单元的p沟道型负载MISFET形成在n型阱区域的字线延伸方向的主表面上，p沟道型负载MISFET的源极区域沿列方向布置的存储单元通过导体层电连接到n型阱区，并且每个导体层独立于沿列方向排列的存储单元而形成。更具体地，n型阱区域被馈送有第一固定电位，并且每个p沟道型负载MISFET的源极区域通过独立形成的导体层馈送第一固定电位。

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