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1. 发明授权

US5661329A Semiconductor integrated circuit device including an improved separating groove arrangement 失效
标题翻译：半导体集成电路器件包括改进的分离槽布置
公开(公告)号：US5661329A
公开(公告)日：1997-08-26
申请号：US350944
申请日：1994-12-07
申请人： Toshiro Hiramoto , Nobuo Tamba , Masami Usami , Takahide Ikeda , Kazuo Tanaka , Atsuo Watanabe , Satoru Isomura , Toshiyuki Kikuchi , Toru Koizumi
发明人： Toshiro Hiramoto , Nobuo Tamba , Masami Usami , Takahide Ikeda , Kazuo Tanaka , Atsuo Watanabe , Satoru Isomura , Toshiyuki Kikuchi , Toru Koizumi
IPC分类号： H01L21/84 , H01L27/12 , H01L29/10 , H01L29/00 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/1079
摘要： A semiconductor integrated circuit device includes an element separating first and second grooves formed to surround active regions to be formed with a semiconductor element. In addition a third groove is formed to surround at least a portion of the first groove, when viewed from a plane view. In the semiconductor integrated circuit device, the active regions and an element separating region of a silicon layer are insulated from each other by the separating grooves extending from the main surface of the silicon layer to an underlying insulating layer, and are fed with a common fixed potential.
摘要翻译：半导体集成电路器件包括分离形成为围绕要形成半导体元件的有源区的第一和第二沟槽的元件。此外，当从平面视图观察时，形成第三凹槽以围绕第一凹槽的至少一部分。在半导体集成电路器件中，硅层的有源区域和元件分离区域通过从硅层的主表面延伸到下面的绝缘层的分离槽彼此绝缘，并且被馈送有公共固定潜在。

2. 发明授权

US5793097A Semiconductor device having conducting structure 失效
标题翻译：具有导电结构的半导体器件
公开(公告)号：US5793097A
公开(公告)日：1998-08-11
申请号：US519096
申请日：1995-08-24
申请人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
发明人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01C7/06 , H01L21/02 , H01L21/822 , H01L27/04 , H01L27/06 , H01L29/00 , H01L23/48 , H01L29/76
CPC分类号： H01L27/0652 , H01L27/0688 , H01L28/20
摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
摘要翻译：本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二多晶层具有负电阻的温度依赖性，反之亦然。此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

3. 发明授权

US07238582B2 Semiconductor device and process of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07238582B2
公开(公告)日：2007-07-03
申请号：US11000092
申请日：2004-12-01
申请人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
发明人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01L21/8222
CPC分类号： H01L27/0652 , H01L27/0688 , H01L28/20
摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
摘要翻译：本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二多晶硅层具有负电阻的温度依赖性，反之亦然。此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

4. 发明申请

US20050101097A1 Semiconductor device and process of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050101097A1
公开(公告)日：2005-05-12
申请号：US11000092
申请日：2004-12-01
申请人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
发明人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01C7/06 , H01L21/02 , H01L21/822 , H01L27/04 , H01L27/06 , H01L21/20 , H01L21/8222
CPC分类号： H01L27/0652 , H01L27/0688 , H01L28/20
摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
摘要翻译：本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二多晶硅层具有负电阻的温度依赖性，反之亦然。此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

5. 发明授权

US6133094A Semiconductor device and process of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US6133094A
公开(公告)日：2000-10-17
申请号：US123405
申请日：1998-07-28
申请人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
发明人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01C7/06 , H01L21/02 , H01L21/822 , H01L27/04 , H01L27/06 , H01L21/336
CPC分类号： H01L27/0652 , H01L27/0688 , H01L28/20
摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
摘要翻译：本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二多晶层具有负电阻的温度依赖性，反之亦然。此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

6. 发明授权

US06835632B2 Semiconductor device and process of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06835632B2
公开(公告)日：2004-12-28
申请号：US10460215
申请日：2003-06-13
申请人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
发明人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01L2120
CPC分类号： H01L27/0652 , H01L27/0688 , H01L28/20
摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
摘要翻译：本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二多晶硅层具有负电阻的温度依赖性，反之亦然。此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

7. 发明授权

US06524924B1 Semiconductor device and process of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06524924B1
公开(公告)日：2003-02-25
申请号：US09123406
申请日：1998-07-28
申请人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
发明人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01L2120
CPC分类号： H01L27/0652 , H01L27/0688 , H01L28/20
摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
摘要翻译：本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。使用包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的至少两层结构，并且第一多晶硅层具有正电温度依赖性而第二多晶层具有电阻的负温度依赖性，反之亦然。此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

8. 发明授权

US5321650A BiCMOS semiconductor memory device using load transistors formed on an insulating film 失效
标题翻译： BiCMOS半导体存储器件使用负载晶体管形成在绝缘膜上
公开(公告)号：US5321650A
公开(公告)日：1994-06-14
申请号：US895682
申请日：1992-06-09
申请人： Toshiyuki Kikuchi , Takahide Ikeda
发明人： Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01L21/8249 , H01L27/06 , H01L27/10 , H01L21/225
CPC分类号： H01L27/0623
摘要： P-channel MOSFETs in a fully CMOS-type memory cell are formed by a thin film (polysilicon), and portions that serve as source and drain regions of the thin-film p-channel MOSFETs are thickened by a conductor layer having a small resistance value. Further, the thin film and the conductor layer having a small resistance value are formed in common with a base lead-out layer of an npn bipolar transistor constituting a peripheral circuit.
摘要翻译：完全CMOS型存储单元中的P沟道MOSFET由薄膜（多晶硅）形成，用作薄膜p沟道MOSFET的源极和漏极区的部分由具有小电阻的导体层增厚值。此外，具有小电阻值的薄膜和导体层与构成外围电路的npn双极晶体管的基极引出层共同形成。

9. 发明授权

US06610569B1 Semiconductor device and process of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06610569B1
公开(公告)日：2003-08-26
申请号：US09649504
申请日：2000-08-28
申请人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
发明人： Hiromi Shimamoto , Takashi Uchino , Takeo Shiba , Kazuhiro Ohnishi , Yoichi Tamaki , Takashi Kobayashi , Toshiyuki Kikuchi , Takahide Ikeda
IPC分类号： H01L21336
CPC分类号： H01L27/0652 , H01L27/0688 , H01L28/20
摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
摘要翻译：本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且多晶第一硅层的抗蚀剂的温度依赖性为正，而第二多晶层具有电阻的负温度依赖性，反之亦然。此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

10. 发明授权

US06200115B1 Scroll type compressor and rotation preventing mechanism used in the same 有权
标题翻译：滚动式压缩机和旋转防止机构
公开(公告)号：US06200115B1
公开(公告)日：2001-03-13
申请号：US09366196
申请日：1999-08-04
申请人： Toshiyuki Kikuchi
发明人： Toshiyuki Kikuchi
IPC分类号： F04C1804
CPC分类号： F01C17/063 , F01C17/06 , F16C2360/42
摘要： A ball coupling constituting a rotation preventing mechanism (77) includes a first annular race section (59, 79) having a thrust ball transfer surface formed on one surface thereof, a second annular race section (61, 81) having a ball transfer surface formed on one surface thereof confronting the one surface of the first race section and thrust balls (67) interposed between the first and second race sections (79, 81). At least one of the first and second race sections has a cross sectional shape such that the central portion of the other surface (87) thereof confronting the one surface is a recessed groove (89). A scroll type compressor includes the rotation preventing mechanism on the back surface of a movable scroll member.
摘要翻译：构成旋转防止机构（77）的球形联轴器包括在其一个表面上形成有推力球转移面的第一环形圈部（59,79），形成有球转移面的第二环形圈部（61,81）在其面对第一座圈部分的一个表面的一个表面上以及置于第一和第二座圈部分（79,81）之间的推力球（67）。第一和第二座圈中的至少一个具有横截面形状，使得面对该一个表面的另一个表面（87）的中心部分是凹槽（89）。涡旋式压缩机包括在可动涡旋件的后表面上的防旋转机构。

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