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1. 发明授权

US5457412A Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals 失效
标题翻译：半导体集成电路器件包括输入电路，以允许具有ECL电平输入信号的Bi-CMOS存储器的操作
公开(公告)号：US5457412A
公开(公告)日：1995-10-10
申请号：US149935
申请日：1993-11-10
申请人： Nobuo Tamba , Masanori Odaka , Toshiro Hiramoto , Masayuki Ohayashi , Kayoko Saito
发明人： Nobuo Tamba , Masanori Odaka , Toshiro Hiramoto , Masayuki Ohayashi , Kayoko Saito
IPC分类号： G11C11/413 , H01L21/8249 , H01L27/06 , H03K19/0175 , H03K19/08
CPC分类号： H03K19/017527
摘要： A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.
摘要翻译：提供了一种半导体集成电路器件，用于允许具有ECL电平输入信号的CMOS或BiCMOS存储器的操作，其中操作速度增加并且功耗降低。 ECL电平的输入信号由输入缓冲器接收，用于将输入信号放大到输入缓冲器的差分晶体管在不饱和区域中操作的范围内的输出信号电平。输入缓冲器的输出信号被提供给CMOS电路或Bi-CMOS电路，该CMOS电路或Bi-CMOS电路由具有比输入缓冲器的工作电压的绝对值小的第一级的工作电压和电路。该第一级CMOS或BiCMOS电路还包括进一步放大接收信号以提供进一步电平转换的装置。由于输入缓冲器和第一级CMOS或Bi-CMOS电路都执行信号传输和电平转换，所以可以通过简单的结构实现高速操作和低功耗。

2. 发明授权

US5255225A Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit 失效
标题翻译：半导体集成电路器件和存储器由半导体集成电路组成
公开(公告)号：US5255225A
公开(公告)日：1993-10-19
申请号：US845557
申请日：1992-03-04
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
IPC分类号： G11C5/14 , G11C7/10 , G11C11/40
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.The speed of an operation of the circuit device can be increased to a high level owing to a simple circuit in which a level, which is required to attain an output amplitude, of complementary output signals is secured by the current switch circuit, the amplified complementary signals being inputted into the emitter follower circuit to directly drive the output transistor.
摘要翻译：提供一种包括电平转换电路的半导体集成电路器件，其中电路的简化和操作速度的提高已经达到。通过包括接收输入信号和参考电压的差分晶体管的电流开关电路将被放大到所需信号电平的一对互补输出信号输入到一对发射极跟随器电路中。射极跟随器输出晶体管由来自一个射极跟随器电路的输出信号驱动，而在输出晶体管和用作负载的电流源之间提供的N沟道MOSFET由另一个射极跟随器电路的输出信号驱动到从输出晶体管的发射极获得电平放大的输出信号。电路装置的运行速度可以通过电流开关电路确保互补输出信号的达到输出幅度所需的电平的简单电路而增加到高电平，放大的互补信号被输入射极跟随器电路以直接驱动输出晶体管。

3. 发明授权

US5519658A Semiconductor integrated circuit device and methods for production thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5519658A
公开(公告)日：1996-05-21
申请号：US332078
申请日：1994-11-01
申请人： Takayuki Uda , Toshiro Hiramoto , Nobuo Tamba , Hisashi Ishida , Kazuhiro Akimoto , Masanori Odaka , Tasuku Tanaka , Jun Hirokawa , Masayuki Ohayashi
发明人： Takayuki Uda , Toshiro Hiramoto , Nobuo Tamba , Hisashi Ishida , Kazuhiro Akimoto , Masanori Odaka , Tasuku Tanaka , Jun Hirokawa , Masayuki Ohayashi
IPC分类号： H01L21/60 , H01L23/055 , H01L23/525 , H01L27/118 , G11C7/00
CPC分类号： H01L24/81 , H01L23/055 , H01L23/5256 , H01L24/11 , H01L27/118 , H01L2224/0401 , H01L2224/05567 , H01L2224/05572 , H01L2224/1147 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/73253 , H01L2224/81801 , H01L23/3171 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/0107 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/19043 , H01L2924/3011 , H01L2924/3025
摘要： Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage. This allows a faulty circuit to be replaced with the corresponding redundancy circuit.
摘要翻译：公开了半导体集成电路装置及其制造方法。本发明的实施例是一种半导体芯片，其包括构成其中形成的冗余电路的一部分的保险丝，该保险丝由相同成分CCB凸块基底金属制成。在CCB凸块基板金属的图案化期间，熔丝同时被图案化。这涉及使用芯片中的电极导体图案的成分的至少一部分来形成保险丝。保险丝的切割区域仅由构成基板的金属层中的一个构成。半导体芯片的主平面具有至少形成在保险丝的切割区域上的保险丝保护膜，用于保护保险丝。在操作中，使用冗余信号的开关控制下的开关MOSFET来选择两个传输路径中的一个，一个传送地址信号或解码信号，另一个传送参考电压。这样可以将故障电路替换为相应的冗余电路。

4. 发明授权

US5360988A Semiconductor integrated circuit device and methods for production thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5360988A
公开(公告)日：1994-11-01
申请号：US903202
申请日：1992-06-23
申请人： Takayuki Uda , Toshiro Hiramoto , Nobuo Tamba , Hisashi Ishida , Kazuhiro Akimoto , Masanori Odaka , Tasuku Tanaka , Jun Hirokawa , Masayuki Ohayashi
发明人： Takayuki Uda , Toshiro Hiramoto , Nobuo Tamba , Hisashi Ishida , Kazuhiro Akimoto , Masanori Odaka , Tasuku Tanaka , Jun Hirokawa , Masayuki Ohayashi
IPC分类号： H01L21/60 , H01L23/055 , H01L23/525 , H01L27/118 , H01L23/48 , F42C19/12 , G06F15/60 , H01L21/285
CPC分类号： H01L24/81 , H01L23/055 , H01L23/5256 , H01L24/11 , H01L27/118 , H01L2224/0401 , H01L2224/05567 , H01L2224/05572 , H01L2224/1147 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/73253 , H01L2224/81801 , H01L23/3171 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/0107 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/19043 , H01L2924/3011 , H01L2924/3025
摘要： Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients as those of a CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage. This allows a faulty circuit to be replaced with the corresponding redundancy circuit.
摘要翻译：公开了半导体集成电路装置及其制造方法。本发明的实施例是一种半导体芯片，其包括构成其中形成的冗余电路的一部分的熔丝，该熔丝由与CCB凸块基板金属相同的部件制成。在CCB凸块基板金属的图案化期间，熔丝同时被图案化。这涉及使用芯片中的电极导体图案的成分的至少一部分来形成保险丝。保险丝的切割区域仅由构成基板的金属层中的一个构成。半导体芯片的主平面具有至少形成在保险丝的切割区域上的保险丝保护膜，用于保护保险丝。在操作中，使用冗余信号的开关控制下的开关MOSFET来选择两个传输路径中的一个，一个传送地址信号或解码信号，另一个传送参考电压。这样可以将故障电路替换为相应的冗余电路。

5. 发明授权

US5354699A Method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5354699A
公开(公告)日：1994-10-11
申请号：US964824
申请日：1992-10-22
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265
CPC分类号： H01L21/28026 , H01L21/28525 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

6. 发明授权

US5512497A Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US5512497A
公开(公告)日：1996-04-30
申请号：US272312
申请日：1994-07-08
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265 , H01L21/8238
CPC分类号： H01L21/28026 , H01L21/28525 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

7. 发明授权

US5057894A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5057894A
公开(公告)日：1991-10-15
申请号：US526696
申请日：1990-05-23
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/285 , H01L21/8249 , H01L27/06
CPC分类号： H01L27/0623 , H01L21/28525 , H01L21/8249
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

8. 发明授权

US4903093A Semiconductor integrated circuit device double isolated CMOS input protection resistor 失效
标题翻译：半导体集成电路器件双隔离CMOS输入保护电阻
公开(公告)号：US4903093A
公开(公告)日：1990-02-20
申请号：US199671
申请日：1988-05-27
申请人： Akira Ide , Koichi Motohashi , Masanori Odaka , Nobuo Tamba
发明人： Akira Ide , Koichi Motohashi , Masanori Odaka , Nobuo Tamba
IPC分类号： H01L21/8249 , H01L21/331 , H01L27/02 , H01L27/06 , H01L27/10 , H01L27/105 , H01L29/73 , H01L29/732
CPC分类号： H01L27/0288 , H01L27/0251 , H01L27/105
摘要： In a semiconductor integrated circuit device, input protective elements have current limiting resistors which are diffused resistors of a second conductivity type formed in a first semiconductor region of a first conductivity type isolated electrically by a second semiconductor region of the second conductivity type, with the first conductivity type semiconductor region being in a floating state electrically. The input protective elements create less leak current and have high electrostatic durability.
摘要翻译：在半导体集成电路器件中，输入保护元件具有限流电阻，其是第二导电类型的扩散电阻器，形成在由第二导电类型的第二半导体区域电隔离的第一导电类型的第一半导体区域中，导电型半导体区域处于浮置状态。输入保护元件产生更少的漏电流并具有高静电耐久性。

9. 发明授权

US5214302A Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove 失效
标题翻译：在公共衬底上形成的半导体集成电路器件通过由沟槽隔离的场氧化物和双极晶体管隔离的MISFET
公开(公告)号：US5214302A
公开(公告)日：1993-05-25
申请号：US807411
申请日：1991-12-13
申请人： Akihisa Uchida , Keiichi Higeta , Nobuo Tamba , Masanori Odaka , Katsumi Ogiue
发明人： Akihisa Uchida , Keiichi Higeta , Nobuo Tamba , Masanori Odaka , Katsumi Ogiue
IPC分类号： H01L27/06 , H01L27/11 , H01L29/732
CPC分类号： H01L29/7325 , H01L27/0623 , H01L27/1112
摘要： A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region. The bipolar transistor is characterized as a self-alignment transistor and that the insulating side wall spacers corresponding to the gate and base (emitter) electrodes are formed by a same lever.
摘要翻译：一种半导体集成电路器件，具有以下结构，其中以下各个区域，即用于形成每个双极晶体管的基极和发射极区域的第一区域，用于形成双极性的集电极导出区域的第二区域晶体管和用于形成每个MISFET的第三区域从半导体衬底的主表面突出，由此可以实现MISFET之间以及这些MISFET与具有相同隔离结构的双极晶体管之间的隔离，并且在与双极晶体管之间的隔离相同的制造步骤。此外，在该器件中，双极晶体管的基极区域电自自对准地连接到形成在主表面上以围绕发射极区域的基极。双极晶体管的特征在于自对准晶体管，并且与栅极和基极（发射极）电极对应的绝缘侧壁间隔物由相同的杆形成。

10. 发明授权

US4977338A High speed bipolar-MOS logic circuit including a series coupled arrangement of a bipolar transistor and a logic block having a MOSFET 失效
标题翻译：包括双极晶体管和具有MOSFET的逻辑块的串联耦合布置的高速双极MOS逻辑电路
公开(公告)号：US4977338A
公开(公告)日：1990-12-11
申请号：US336425
申请日：1989-04-11
申请人： Shuuichi Miyaoka , Masanori Odaka , Katsumi Ogiue
发明人： Shuuichi Miyaoka , Masanori Odaka , Katsumi Ogiue
IPC分类号： H01L27/06 , H01L21/8249 , H03K17/567 , H03K19/00 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/0008 , H03K19/09448
摘要： A high-speed bipolar MOS logic circuit is provided which includes a load resistance coupled between a first power supply voltage terminal and an output terminal and a bipolar transistor having a collector coupled to said output terminal and a base for receiving a predetermined voltage or an input signal a logic block is also provided including one or more MOSFETs having a source-drain path coupled in series between the emitter of said bipolar transistor and a second power supply voltage terminal.
摘要翻译：提供了一种高速双极MOS逻辑电路，其包括耦合在第一电源电压端子和输出端子之间的负载电阻和耦合到所述输出端子的集电极和用于接收预定电压或输入的基极的双极晶体管信号还包括一个逻辑块，包括一个或多个MOSFET，它们具有串联连接在所述双极晶体管的发射极和第二电源电压端之间的源极 - 漏极通路。

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