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1. 发明授权

US5691952A Semiconductor memory device and memory module using the same 失效
标题翻译：半导体存储器件和使用其的存储器模块
公开(公告)号：US5691952A
公开(公告)日：1997-11-25
申请号：US590608
申请日：1996-01-24
申请人： Toshio Sasaki , Kazumasa Yanagisawa , Toshio Sugano , Kiyoshi Inoue , Seiichiro Tsukui , Masakazu Aoki , Shigeru Suzuki , Masashi Horiguchi
发明人： Toshio Sasaki , Kazumasa Yanagisawa , Toshio Sugano , Kiyoshi Inoue , Seiichiro Tsukui , Masakazu Aoki , Shigeru Suzuki , Masashi Horiguchi
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/108 , G11C13/00
CPC分类号： G11C29/80 , G11C29/74 , G11C29/808 , G11C29/832
摘要： Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.
摘要翻译：第一半导体存储器件的输入/输出端子，其中存在以存储器单元为单位的故障或缺陷，并且具有冗余存储器垫的第二半导体存储器件的输入/输出端子在安装的基板上彼此连接，从而减轻故障在记忆垫单位。电源基本上被切断供给故障存储器垫。

2. 发明授权

US5818792A Semiconductor memory device and memory module using the same 失效
标题翻译：半导体存储器件和使用其的存储器模块
公开(公告)号：US5818792A
公开(公告)日：1998-10-06
申请号：US804683
申请日：1997-02-25
申请人： Toshio Sasaki , Kazumasa Yanagisawa , Toshio Sugano , Kiyoshi Inoue , Seiichiro Tsukui , Masakazu Aoki , Shigeru Suzuki , Masashi Horiguchi
发明人： Toshio Sasaki , Kazumasa Yanagisawa , Toshio Sugano , Kiyoshi Inoue , Seiichiro Tsukui , Masakazu Aoki , Shigeru Suzuki , Masashi Horiguchi
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/108 , G01C13/00
CPC分类号： G11C29/80 , G11C29/74 , G11C29/808 , G11C29/832
摘要： Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.
摘要翻译：第一半导体存储器件的输入/输出端子，其中存在以存储器单元为单位的故障或缺陷，并且具有冗余存储器垫的第二半导体存储器件的输入/输出端子在安装的基板上彼此连接，从而减轻故障在记忆垫单位。电源基本上被切断供给故障存储器垫。

3. 发明授权

US4942556A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4942556A
公开(公告)日：1990-07-17
申请号：US377181
申请日：1989-07-10
申请人： Toshio Sasaki , Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Toshiaki Masuhara
发明人： Toshio Sasaki , Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Toshiaki Masuhara
IPC分类号： G11C15/04 , G11C29/00 , G11C29/44
CPC分类号： G11C29/76 , G11C15/04 , G11C15/046 , G11C29/44
摘要： In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.
摘要翻译：在通过备用存储器单元代替半导体存储器件的缺陷存储单元的缺陷解除技术中，使用关联存储器。存储有缺陷的存储单元的地址信息被存储为关联存储器的参考数据，并且备用存储单元的新地址信息被写入作为关联存储器的输出数据。对联想记忆进行了各种改进。例如，关联存储器的多个符合检测信号线被划分为至少两组，其中一组由切换装置选择。关联存储器的参考数据包括由“0”和“1”的二进制信息组成的三个值，并且不关心值“X”。关联存储器还包括多个可电可编程的非易失性半导体存储器元件。

4. 发明授权

US06643182B2 Semiconductor device 有权
公开(公告)号：US06643182B2
公开(公告)日：2003-11-04
申请号：US10245328
申请日：2002-09-18
申请人： Kazumasa Yanagisawa , Toshio Sasaki , Satoru Nakanishi , Yoshihiko Yasu
发明人： Kazumasa Yanagisawa , Toshio Sasaki , Satoru Nakanishi , Yoshihiko Yasu
IPC分类号： G11C700
CPC分类号： G11C11/4091 , G11C5/025 , G11C7/065
摘要： A dynamic RAM includes sense amplifiers each formed of a latch circuit consisting of MOSFETs of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair which is connected with a number of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a pair of second bit lines provided commonly to a plurality of the first bit line pair in response to the reception of the select signal. The switching MOSFETs have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs of the first conductivity type of the latch circuits, and the select signal has its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.

5. 发明授权

US06301184B1 Semiconductor integrated circuit device having an improved operation control for a dynamic memory 失效
标题翻译：具有用于动态存储器的改进的操作控制的半导体集成电路器件
公开(公告)号：US06301184B1
公开(公告)日：2001-10-09
申请号：US09480695
申请日：2000-01-11
申请人： Toshio Sasaki , Yoshihiko Yasu , Kazumasa Yanagisawa , Yuji Tanaka , Toshiaki Takahira , Yasuto Igarashi , Mariko Ohtsuka , Yasunobu Aoki
发明人： Toshio Sasaki , Yoshihiko Yasu , Kazumasa Yanagisawa , Yuji Tanaka , Toshiaki Takahira , Yasuto Igarashi , Mariko Ohtsuka , Yasunobu Aoki
IPC分类号： G11C800
CPC分类号： G11C11/4074 , G11C7/1045
摘要： A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.
摘要翻译：将DRAM模块应用于具有用于抑制其整体操作的待机模式的系统LSI和至少允许DRAM模块操作但抑制其它电路的操作的操作待机模式。将上述模式以及衬底偏置控制技术应用于在低电压下工作的CMOS系统LSI。控制系统LSI以保持或不保存数据，使得能够安装大容量的存储器并消耗足够的电力量。

6. 发明授权

US06480425B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06480425B2
公开(公告)日：2002-11-12
申请号：US09820972
申请日：2001-03-30
申请人： Kazumasa Yanagisawa , Toshio Sasaki , Satoru Nakanishi , Yoshihiko Yasu
发明人： Kazumasa Yanagisawa , Toshio Sasaki , Satoru Nakanishi , Yoshihiko Yasu
IPC分类号： G11C700
CPC分类号： G11C11/4091 , G11C5/025 , G11C7/065
摘要： A dynamic RAM includes sense amplifiers each formed of a latch circuit consisting of MOSFETs of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair which is connected with a number of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a pair of second bit lines provided commonly to a plurality of the first bit line pair in response to the reception of the select signal. The switching MOSFETs have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs of the first conductivity type of the latch circuits, and the select signal has its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.
摘要翻译：动态RAM包括读出放大器，每个读出放大器分别由一个由第一和第二导电类型的MOSFET构成的锁存电路构成，并分别对其源极施加第一和第二电压，并具有一对输入/输出节点第一位线对与多个动态存储单元连接，并且还包括成对的第一导电类型的开关MOSFET，其选择性地将锁存电路的输入/输出节点对连接到一对共同设置的第二位线多个第一位线对响应于该选择信号的接收。开关MOSFET的阈值电压设置为比第一导电类型的锁存电路的MOSFET的阈值电压的绝对值小，并且选择信号具有关闭开关MOSFET的电平，该开关MOSFET的绝对值设定得更大相对于第二电压的第一电压值。

7. 发明授权

US6091660A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US6091660A
公开(公告)日：2000-07-18
申请号：US376468
申请日：1999-08-18
申请人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
发明人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
IPC分类号： G11C11/401 , G11C8/00 , G11C8/12 , G11C11/407
CPC分类号： G11C8/12
摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
摘要翻译：安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。分别提供用于分别执行+1或-1算术运算的算术电路，以便对应于相应的存储器垫并且以级联形式电连接。初始级算术电路的输入端被提供地址设定固定地址信号。提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。基于所得到的一致信号来选择相应的存储器垫。

8. 发明授权

US06314044B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06314044B1
公开(公告)日：2001-11-06
申请号：US09594840
申请日：2000-06-15
申请人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
发明人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
摘要翻译：安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。分别提供用于分别执行+1或-1运算的算术电路，以对应于相应的存储器垫并且以级联形式电连接。初始级算术电路的输入端被提供地址设定固定地址信号。提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。基于所得到的一致信号来选择相应的存储器垫。

9. 发明授权

US5978305A Semiconductor integrated circuit device 失效
公开(公告)号：US5978305A
公开(公告)日：1999-11-02
申请号：US165194
申请日：1998-10-02
申请人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
发明人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
IPC分类号： G11C11/401 , G11C8/00 , G11C8/12 , G11C11/407 , G11C7/00
CPC分类号： G11C8/12
摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

10. 发明授权

US08421527B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08421527B2
公开(公告)日：2013-04-16
申请号：US13562157
申请日：2012-07-30
申请人： Toshio Sasaki , Kazuki Fukuoka , Ryo Mori , Yoshihiko Yasu
发明人： Toshio Sasaki , Kazuki Fukuoka , Ryo Mori , Yoshihiko Yasu
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , G06F1/3203 , G06F1/3287 , H01L27/0207 , H01L27/088 , H01L2224/48091 , H01L2924/13091 , Y02D10/171 , Y02D50/20 , H01L2924/00014 , H01L2924/00
摘要： The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.
摘要翻译：本发明旨在在低功耗结构中大幅度地提高电路布局面积的同时执行精细的低电压控制。在将区域移动到低速模式的情况下，系统控制器分别向功率开关控制器和低功率驱动电路输出请求信号和使能信号，以关闭电源开关并执行控制使得虚拟参考电位的电压电平变为约0.2V至约0.3V。该区域在电源电压和虚拟参考电位之间的电压下工作，使得其在低速模式下被控制。

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