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1. 发明授权

US4942556A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4942556A
公开(公告)日：1990-07-17
申请号：US377181
申请日：1989-07-10
申请人： Toshio Sasaki , Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Toshiaki Masuhara
发明人： Toshio Sasaki , Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Toshiaki Masuhara
IPC分类号： G11C15/04 , G11C29/00 , G11C29/44
CPC分类号： G11C29/76 , G11C15/04 , G11C15/046 , G11C29/44
摘要： In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.
摘要翻译：在通过备用存储器单元代替半导体存储器件的缺陷存储单元的缺陷解除技术中，使用关联存储器。存储有缺陷的存储单元的地址信息被存储为关联存储器的参考数据，并且备用存储单元的新地址信息被写入作为关联存储器的输出数据。对联想记忆进行了各种改进。例如，关联存储器的多个符合检测信号线被划分为至少两组，其中一组由切换装置选择。关联存储器的参考数据包括由“0”和“1”的二进制信息组成的三个值，并且不关心值“X”。关联存储器还包括多个可电可编程的非易失性半导体存储器元件。

2. 发明授权

US4701884A Semiconductor memory for serial data access 失效
标题翻译：用于串行数据访问的半导体存储器
公开(公告)号：US4701884A
公开(公告)日：1987-10-20
申请号：US896257
申请日：1986-08-14
申请人： Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Katsuhiro Shimohigashi , Toshiaki Masuhara , Kiyoo Itoh , Hideo Nakamura , Osamu Minato
发明人： Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Katsuhiro Shimohigashi , Toshiaki Masuhara , Kiyoo Itoh , Hideo Nakamura , Osamu Minato
IPC分类号： G11C11/56 , H01L27/108 , G11C13/00
CPC分类号： G11C11/565 , H01L27/10805
摘要： A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided. The feature of this device lies in that the voltage generator for serially generating three or more values of the voltage which are different from each other and the means for applying said voltage to said memory cells are provided on the same semiconductor board as the same said memory cells, and as the said reading mechanism the column register is provided which, as said reading mechanism, has the mechanism for deciding the data, transfer gate which is provided between said deciding means and said data line, and the bias charge transfer mechanism which is provided between said transfer gate and said deciding mechanism, and having at least two or more memory elements for temporarily storing said decided data.
摘要翻译：提出了一种半导体存储器件，其中至少包括多个具有至少一个容量的存储单元的阵列，用于指定每个存储单元的位置的选择机构，连接到所述存储器单元的用于发送数据的数据线和数据提供写入和数据读取机制。该装置的特征在于，用于串联产生彼此不同的三个或更多个电压值的电压发生器和用于将所述电压施加到所述存储单元的装置设置在与所述存储器相同的半导体板上并且作为所述读取机构，列寄存器被提供，其作为所述读取机构具有用于确定数据的机制，所述决定装置和所述数据线之间提供的传送门和作为所述读取机构的偏置电荷传送机构提供在所述传送门和所述判定机构之间，并且具有用于临时存储所述决定的数据的至少两个或更多个存储器元件。

3. 发明授权

US4709350A Semiconductor memory using multiple level storage structure 失效
标题翻译：半导体存储器采用多级存储结构
公开(公告)号：US4709350A
公开(公告)日：1987-11-24
申请号：US627895
申请日：1984-07-05
申请人： Yoshinobu Nakagome , Masakazu Aoki , Masashi Horiguchi , Katsuhiro Shimohigashi , Shinichi Ikenaga
发明人： Yoshinobu Nakagome , Masakazu Aoki , Masashi Horiguchi , Katsuhiro Shimohigashi , Shinichi Ikenaga
IPC分类号： G11C14/00 , G11C11/56 , G11C19/00 , G11C27/00
CPC分类号： G11C19/00 , G11C11/565 , G11C8/04
摘要： In a semiconductor memory for reading and writing of stored charge in an X-Y address system by arranging a plurality of memory cells each including a capacitance element and one MOS-FET in matrix, this invention discloses a semiconductor memory using multiple level storage structure for read and write of at least more than two multi-level data stored in the capacitance elements, by applying a multi-level step voltage to the plate electrode of the capacitance or to the gate electrode of MOS-FET so as to write and read signal charge.
摘要翻译：在通过将包括电容元件和一个MOS-FET的多个存储单元布置在矩阵中的用于在XY地址系统中读取和写入存储电荷的半导体存储器中，本发明公开了一种使用多级存储结构进行读取和通过对电容器的平板电极或MOS-FET的栅电极施加多电平阶梯电压以写入和读取信号电荷，写入存储在电容元件中的至少两个多电平数据。

4. 发明授权

US4726021A Semiconductor memory having error correcting means 失效
标题翻译：具有误差校正装置的半导体存储器
公开(公告)号：US4726021A
公开(公告)日：1988-02-16
申请号：US853230
申请日：1986-04-17
申请人： Masashi Horiguchi , Masakazu Aoki , Yoshinobu Nakagome , Shinichi Ikenaga , Katsuhiro Shimohigashi
发明人： Masashi Horiguchi , Masakazu Aoki , Yoshinobu Nakagome , Shinichi Ikenaga , Katsuhiro Shimohigashi
IPC分类号： G06F11/10 , G11C29/24 , G01R31/28
CPC分类号： G06F11/1008 , G06F11/1076 , G11C29/24
摘要： A semiconductor memory having an error correcting function is provided, which has a device by which the user finds no difficulty in making use of the semiconductor memory and can test it with ease. In the semiconductor memory, a signal indicative of the completion of the preparation for reading/writing is outputted from the memory so that the user, after detecting the output of this signal, performs reading/writing data. To facilitate tests, such as a memory cell test for a redundant bit (check bit), an encoding circuit test and a decoding circuit test, the present invention provides that the arranged tests can be made independently of each other.
摘要翻译：提供了具有纠错功能的半导体存储器，其具有用户不用利用半导体存储器并且可以容易地进行测试的装置。在半导体存储器中，从存储器输出表示完成读/写准备的信号，使得用户在检测到该信号的输出之后，执行读/写数据。为了便于诸如用于冗余位（校验位）的存储器单元测试，编码电路测试和解码电路测试的测试，本发明提供了可以彼此独立地进行布置的测试。

5. 发明授权

US4661929A Semiconductor memory having multiple level storage structure 失效
标题翻译：具有多级存储结构的半导体存储器
公开(公告)号：US4661929A
公开(公告)日：1987-04-28
申请号：US686018
申请日：1984-12-24
申请人： Masakazu Aoki , Yoshinobu Nakagome , Masashi Horiguchi , Shinichi Ikenaga , Katsuhiro Shimohigashi
发明人： Masakazu Aoki , Yoshinobu Nakagome , Masashi Horiguchi , Shinichi Ikenaga , Katsuhiro Shimohigashi
IPC分类号： G06F11/10 , G11C7/06 , G11C11/4091 , G11C11/56 , G11C11/40
CPC分类号： G11C11/565 , G11C11/4091 , G11C7/065 , G06F11/1072 , G11C29/00 , G11C7/06
摘要： In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.
摘要翻译：在半导体存储器中，包括由分别具有至少一个存储电容器的多个存储器单元组成的存储器阵列，指定每个存储单元的位置的寻址电路，发送连接到所述存储单元的数据的数据线和数据写入和读取电路连接到所述数据线。半导体存储器具有多级存储结构。具体而言，该存储器包括用于按时间序列依次将至少3级以上的不同电压施加到所述存储单元的开关型MOS晶体管的栅极的装置，作为所述数据读取电路的偏置电荷供给装置以及提供临时存储所述数据的至少两个或更多个存储单元的列寄存器。

6. 发明授权

US4949306A Sense circuit and semiconductor memory having a current-voltage converter circuit 失效
标题翻译：检测电路和具有电流 - 电压转换器电路的半导体存储器
公开(公告)号：US4949306A
公开(公告)日：1990-08-14
申请号：US201015
申请日：1988-06-01
申请人： Yoshinobu Nakagome , Masakazu Aoki , Masashi Horiguchi , Kiyoo Itoh , Shinichi Ikenaga
发明人： Yoshinobu Nakagome , Masakazu Aoki , Masashi Horiguchi , Kiyoo Itoh , Shinichi Ikenaga
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G11C7/1048 , G11C7/062
摘要： A highly integrated memory features increased reading speed and writing speed. A sense circuit for this memory including a memory cell array having a plurality of memory cells each of which including at least one insulated gate field effect transistor, and a plurality of data lines to which the memory cells are connected. The memory also includes an address selection mechanism which is capable of selecting a memory cell out of a plurality of memory cells and connecting it to the data line. A sense amplifier a mechanism which is connected to the data line and amplifies a voltage according to the data of a memory cell. A common line (input/output line) is connected to the data lines, via a column switch, where the selection depends upon a column address. A main amplifier is connected to the common line (input/output line), and has at least a mechanism for stabilizing the voltage of the common line (input/output line) and an amplifying mechanism.
摘要翻译：高度集成的内存具有更高的读取速度和写入速度。一种用于该存储器的感测电路，包括具有多个存储单元的存储单元阵列，每个存储单元包括至少一个绝缘栅场效应晶体管和存储单元连接到的多条数据线。存储器还包括地址选择机制，其能够从多个存储器单元中选择存储单元并将其连接到数据线。读出放大器，连接到数据线并根据存储单元的数据放大电压的机构。公共线路（输入/输出线路）通过列开关连接到数据线，其中选择取决于列地址。主放大器连接到公共线（输入/输出线），并且至少具有用于稳定公共线（输入/输出线）的电压和放大机构的机构。

7. 发明授权

US4636985A Semiconductor memory having charge transfer device voltage amplifier 失效
标题翻译：具有电荷转移装置电压放大器的半导体存储器
公开(公告)号：US4636985A
公开(公告)日：1987-01-13
申请号：US648361
申请日：1984-09-07
申请人： Masakazu Aoki , Yoshinobu Nakagome , Masahi Horiguchi , Toshifumi Ozaki , Katsuhiro Shimohigashi , Shinichi Ikenaga
发明人： Masakazu Aoki , Yoshinobu Nakagome , Masahi Horiguchi , Toshifumi Ozaki , Katsuhiro Shimohigashi , Shinichi Ikenaga
IPC分类号： G11C7/06 , G11C7/22 , H01L27/108 , G11C7/00
CPC分类号： G11C7/22 , G11C7/06 , H01L27/108
摘要： In a semiconductor memory in which a large number of memory cells are arrayed in the shape of a matrix, arrangements are provided for a high-sensitivity read-out. In one embodiment, a writing circuit, a voltage amplifier and a sense amplifier are successively connected to a data line that connects input and output ends of the memory cells in an identical row, with the voltage amplifier being formed as a CTD voltage amplifier that is composed of two charge transfer gates and a driving gate located between them. In accordance with another embodiment, a charge supplying circuit and a charge transfer circuit can be coupled between the memory cells and the sense amplifier to allow information transfer without any substantial loss.
摘要翻译：在其中以矩阵形式排列大量存储单元的半导体存储器中，提供了用于高灵敏度读出的布置。在一个实施例中，写入电路，电压放大器和读出放大器连续地连接到连接存储器单元的输入和输出端相同行的数据线，电压放大器形成为CTD电压放大器由两个电荷转移门和位于它们之间的驱动门组成。根据另一个实施例，电荷供应电路和电荷转移电路可以耦合在存储器单元和读出放大器之间以允许信息传输而没有任何实质的损失。

8. 发明申请

US20070242535A1 Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US20070242535A1
公开(公告)日：2007-10-18
申请号：US11714867
申请日：2007-03-07
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C7/10
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
摘要翻译：形成在半导体芯片上的半导体存储器件包括第一存储器阵列，多个第二存储器阵列，第一电压发生器和第一焊盘。半导体芯片被分为第一，第二和第三矩形区域，第三矩形区域布置在第一矩形区域和第二矩形区域之间。第一存储器阵列形成在第一矩形区域中。第二存储器阵列形成在第二矩形区域中。电压发生器和第一接合焊盘布置在第三矩形区域中。第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和第二存储器阵列之间没有布置接合焊盘。

9. 发明授权

US6160744A Semiconductor memory device and defect remedying method thereof 有权
公开(公告)号：US6160744A
公开(公告)日：2000-12-12
申请号：US361203
申请日：1999-07-27
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C5/00 , G11C5/02 , G11C5/06 , G11C11/34 , G11C11/406 , H01L23/485 , G11C13/00
CPC分类号： G11C5/025 , G11C5/063 , G11C11/406 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

10. 发明授权

US5602771A Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US5602771A
公开(公告)日：1997-02-11
申请号：US159621
申请日：1993-12-01
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C5/00 , G11C5/02 , G11C5/06 , G11C11/34 , G11C11/406 , H01L23/485
CPC分类号： G11C5/025 , G11C11/406 , G11C5/063 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/73215 , H01L24/45 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01033 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01087 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025
摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
摘要翻译：这里公开了一种半导体存储器件，其中外围电路布置在由纵向中心部分和横向中心部分组成的半导体芯片的交叉区域中，并且其中存储器阵列布置在由交叉区域。由于外围电路布置在芯片的中心部分的这种结构，最长的信号传输路径可以缩短到芯片尺寸的大约一半，以加快DRAM的大容量。

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