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    • 6. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US07245521B2
    • 2007-07-17
    • US11169800
    • 2005-06-30
    • Ryo MoriToshio YamadaTetsuya Muraya
    • Ryo MoriToshio YamadaTetsuya Muraya
    • G11C11/00G11C5/14
    • G11C11/412
    • The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed. In the standby state, the substrate bias switching circuit supplies a predetermined voltage which is lower than the power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased to the N-type well, and supplies a predetermined voltage which is higher than the ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased to the P-type well.
    • 本发明提供一种半导体集成电路器件,其具有泄漏电流降低的SRAM。 在包括多个存储单元的SRAM中,每个存储单元由两个反相器电路的输入和输出端子交叉存储的存储器构成,以及设置在存储和互补位线之间并且其栅极连接到字线的选择MOSFET, 提供了衬底偏置开关电路。 在正常操作中,衬底偏置开关电路将电源电压提供给形成存储单元的P沟道MOSFET的N型阱,并将电路的接地电位提供给P型阱,其中, 形成N沟道MOSFET。 在待机状态下,衬底偏置开关电路提供低于电源电压的预定电压,并且N型阱和P沟道MOSFET的源极之间的PN结不被正向偏置到N 并且提供比地电位高的预定电压,并且P型阱和N沟道MOSFET的源极之间的PN结未被正向偏置到P型阱。