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1. 发明授权

US06314044B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06314044B1
公开(公告)日：2001-11-06
申请号：US09594840
申请日：2000-06-15
申请人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
发明人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
摘要翻译：安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。分别提供用于分别执行+1或-1运算的算术电路，以对应于相应的存储器垫并且以级联形式电连接。初始级算术电路的输入端被提供地址设定固定地址信号。提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。基于所得到的一致信号来选择相应的存储器垫。

2. 发明授权

US5978305A Semiconductor integrated circuit device 失效
公开(公告)号：US5978305A
公开(公告)日：1999-11-02
申请号：US165194
申请日：1998-10-02
申请人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
发明人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
IPC分类号： G11C11/401 , G11C8/00 , G11C8/12 , G11C11/407 , G11C7/00
CPC分类号： G11C8/12
摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

3. 发明授权

US6091660A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US6091660A
公开(公告)日：2000-07-18
申请号：US376468
申请日：1999-08-18
申请人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
发明人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
IPC分类号： G11C11/401 , G11C8/00 , G11C8/12 , G11C11/407
CPC分类号： G11C8/12
摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
摘要翻译：安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。分别提供用于分别执行+1或-1算术运算的算术电路，以便对应于相应的存储器垫并且以级联形式电连接。初始级算术电路的输入端被提供地址设定固定地址信号。提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。基于所得到的一致信号来选择相应的存储器垫。

4. 发明授权

US06643182B2 Semiconductor device 有权
公开(公告)号：US06643182B2
公开(公告)日：2003-11-04
申请号：US10245328
申请日：2002-09-18
申请人： Kazumasa Yanagisawa , Toshio Sasaki , Satoru Nakanishi , Yoshihiko Yasu
发明人： Kazumasa Yanagisawa , Toshio Sasaki , Satoru Nakanishi , Yoshihiko Yasu
IPC分类号： G11C700
CPC分类号： G11C11/4091 , G11C5/025 , G11C7/065
摘要： A dynamic RAM includes sense amplifiers each formed of a latch circuit consisting of MOSFETs of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair which is connected with a number of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a pair of second bit lines provided commonly to a plurality of the first bit line pair in response to the reception of the select signal. The switching MOSFETs have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs of the first conductivity type of the latch circuits, and the select signal has its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.

5. 发明授权

US06480425B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06480425B2
公开(公告)日：2002-11-12
申请号：US09820972
申请日：2001-03-30
申请人： Kazumasa Yanagisawa , Toshio Sasaki , Satoru Nakanishi , Yoshihiko Yasu
发明人： Kazumasa Yanagisawa , Toshio Sasaki , Satoru Nakanishi , Yoshihiko Yasu
IPC分类号： G11C700
CPC分类号： G11C11/4091 , G11C5/025 , G11C7/065
摘要： A dynamic RAM includes sense amplifiers each formed of a latch circuit consisting of MOSFETs of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair which is connected with a number of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a pair of second bit lines provided commonly to a plurality of the first bit line pair in response to the reception of the select signal. The switching MOSFETs have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs of the first conductivity type of the latch circuits, and the select signal has its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.
摘要翻译：动态RAM包括读出放大器，每个读出放大器分别由一个由第一和第二导电类型的MOSFET构成的锁存电路构成，并分别对其源极施加第一和第二电压，并具有一对输入/输出节点第一位线对与多个动态存储单元连接，并且还包括成对的第一导电类型的开关MOSFET，其选择性地将锁存电路的输入/输出节点对连接到一对共同设置的第二位线多个第一位线对响应于该选择信号的接收。开关MOSFET的阈值电压设置为比第一导电类型的锁存电路的MOSFET的阈值电压的绝对值小，并且选择信号具有关闭开关MOSFET的电平，该开关MOSFET的绝对值设定得更大相对于第二电压的第一电压值。

6. 发明授权

US08755585B2 X-ray computed tomography apparatus 有权
标题翻译： X射线计算机断层摄影装置
公开(公告)号：US08755585B2
公开(公告)日：2014-06-17
申请号：US13107368
申请日：2011-05-13
申请人： Satoru Nakanishi , Yasuhiro Noshi
发明人： Satoru Nakanishi , Yasuhiro Noshi
IPC分类号： G06K9/00
CPC分类号： A61B6/5258 , A61B6/032 , A61B6/583 , G06T11/006
摘要： According to one embodiment, an X-ray computed tomography apparatus includes an X-ray tube, an X-ray detector, and a rotating unit. The first reconstruction processing reconstructs a clinical image based on projection data detected by the X-ray detector. The second reconstruction processing reconstructs a noise image based on noise data. The clinical image is combined with the noise image.
摘要翻译：根据一个实施例，X射线计算机断层摄影装置包括X射线管，X射线检测器和旋转单元。第一重建处理基于由X射线检测器检测到的投影数据重建临床图像。第二重建处理基于噪声数据重建噪声图像。临床图像与噪声图像相结合。

7. 发明授权

US08709193B2 Method of manufacturing adhesive-free laminate of aramid paper and polyphenylene sulfide film, and insulation material and insulation structure for rotating electric machinery 有权
标题翻译：芳纶纸和聚苯硫醚薄膜的无粘合剂层压体的制造方法，旋转电机的绝缘材料和绝缘结构
公开(公告)号：US08709193B2
公开(公告)日：2014-04-29
申请号：US12511180
申请日：2009-07-29
申请人： Kenichirou Tada , Satoru Nakanishi , Taku Yamaga , Shun Ito , Kenichi Watanabe , Miyoshi Yokura , Masashi Kato , Hisashi Katsumata
发明人： Kenichirou Tada , Satoru Nakanishi , Taku Yamaga , Shun Ito , Kenichi Watanabe , Miyoshi Yokura , Masashi Kato , Hisashi Katsumata
IPC分类号： B32B37/00
CPC分类号： B32B38/0008 , B32B27/10 , B32B27/16 , B32B27/286 , B32B37/10 , B32B37/1054 , B32B2037/0092 , B32B2262/0269 , B32B2262/14 , B32B2305/076 , B32B2307/206 , B32B2307/208 , B32B2309/02 , B32B2309/105 , B32B2309/12 , B32B2309/72 , B32B2317/12 , B32B2367/00 , B32B2605/00 , H01B3/301 , Y10T428/31725
摘要： A low-temperature plasma treatment is applied to a surface of an aramid paper so as to allow the surface to have a compositional atomic ratio X (O/C) of the number of oxygen atoms (O) to the number of carbon atoms (C) ranging from 110% to 220% of a theoretical atomic ratio. The treatment is performed at an intensity ranging from 120 to 1500 W·min/m2 with a low-temperature plasma treatment apparatus of internal electrode system. The aramid paper is superposed with a nonhydrolyzable resin film and the resulting article is pressurized to give an aramid-resin film laminate. The laminate is inexpensive, has both superior electrical properties and high mechanical strength, excels in elasticity, and is useful as an insulation material.
摘要翻译：将低温等离子体处理施加到芳族聚酰胺纸的表面，以使表面具有氧原子数（O）与碳原子数（C）的组成原子比X（O / C））为理论原子比的110％至220％。用内部电极系统的低温等离子体处理装置，以120〜1500W·min / m 2的强度进行处理。将芳族聚酰胺纸与不可水解的树脂膜重叠，并将所得制品加压，得到芳族聚酰胺树脂膜层压体。该层压板是廉价的，具有优异的电性能和高机械强度，弹性优异，并且可用作绝缘材料。

8. 发明授权

US08693784B2 Eyelid detection device and program 有权
标题翻译：眼睑检测装置及程序
公开(公告)号：US08693784B2
公开(公告)日：2014-04-08
申请号：US13805597
申请日：2011-07-06
申请人： Akira Kadoya , Satoru Nakanishi , Shinichi Kojima
发明人： Akira Kadoya , Satoru Nakanishi , Shinichi Kojima
IPC分类号： G06K9/48 , G06K9/46 , G06K9/40 , G06K9/00
CPC分类号： G06K9/0061 , G06K9/00597 , G06K9/4623 , G06T7/12 , G06T2207/30041 , G06T2207/30201
摘要： An eyelid detection device that, based on first order differential values and second order differential values of vertical density change at an eyelid boundary in an eye image, shifts the second order differential values upwards by ¼ of the cycle of density change frequency of an eyelid boundary and combines the first order differential values and the second order differential values to compute upper eyelid feature amounts. The eyelid detection device detects a boundary between an upper eyelid and eyeball based on peak points in the vertical direction of the computed upper eyelid feature amounts. Consequently, the boundary between an eyelid and eyeball can be accurately detected even when the eyelid has been applied with makeup.
摘要翻译：一种眼睑检测装置，其基于眼图中的眼睑边界处的垂直密度变化的一阶微分值和二阶微分值，将二阶微分值向上移动眼睑边界的密度变化频率周期的1/4 并组合一阶微分值和二阶微分值以计算上眼睑特征量。眼睑检测装置基于计算的上眼睑特征量的垂直方向上的峰值点来检测上眼睑和眼球之间的边界。因此，即使当眼睑已经被化妆时，也能够精确地检测眼睑和眼球之间的边界。

9. 发明授权

US08331630B2 Face feature point detection device and program 有权
标题翻译：面部特征点检测装置和程序
公开(公告)号：US08331630B2
公开(公告)日：2012-12-11
申请号：US13259065
申请日：2010-03-26
申请人： Satoru Nakanishi , Yoshiki Ninomiya , Takashi Naito , Shinichi Kojima , Yoshinao Takemae , Takuhiro Omi , Jun Adachi , Takashi Hiramaki
发明人： Satoru Nakanishi , Yoshiki Ninomiya , Takashi Naito , Shinichi Kojima , Yoshinao Takemae , Takuhiro Omi , Jun Adachi , Takashi Hiramaki
IPC分类号： G06K9/00 , G06K9/46
CPC分类号： G06K9/00281 , G06T7/73
摘要： Detecting with good precision an eye inside corner position and an eye outside corner position as face feature points even when the eye inside corner and/or the eye outside corner portions are obscured by noise. First eyelid profile modeling is performed with a Bezier curve expressed by a fixed control point P3 indicating an eye inside corner first position detected in an image, a fixed control point P4 indicating an eye outside corner first position, a control point P1 corresponding to an upper eyelid position candidate (first parameter), and a control point P2 corresponding to a lower eyelid position candidate (second parameter). Then in a second eyelid profile model with fixed P1 and P2 of the first eyelid profile model having the highest fitting evaluation value λ to the eyelid profile in the image, the values of a control point P3 indicating an eye inside corner position candidate (third parameter) and a control point P4 indicating an eye outside corner candidate (fourth parameter) at a maximum of a fitting evaluation value λ when changing the values of the control point P3 and control point P4 are determined as an eye inside corner second position and an eye outside corner second position, respectively.
摘要翻译：即使当角落内部的眼睛和/或眼睛的外角部被噪声遮蔽时，以高精度检测眼内角位置和眼外角位置作为面部特征点。用固定控制点P3表示的Bezier曲线进行第一次眼皮轮廓建模，所述固定控制点P3表示在图像中检测到的角内第一位置内的眼睛，指示眼睛外角角位置的眼睛的固定控制点P4，对应于上部眼睑位置候选（第一参数）和对应于下眼睑位置候选的控制点P2（第二参数）。然后，在具有对图像中的眼睑轮廓具有最高拟合评估值λ的第一眼睑轮廓模型的具有固定的P1和P2的第二眼睑轮廓模型中，指示角内位置候选中的眼睛的控制点P3的值（第三参数）和将控制点P3和控制点P4的值改变时，以拟合评估值λ的最大值指示眼睛外角候选（第四参数）的控制点P4被确定为眼角内第二位置和眼睛外角第二位。

10. 发明申请

US20120036310A1 DATA PROCESSING DEVICE 审中-公开
标题翻译：数据处理设备
公开(公告)号：US20120036310A1
公开(公告)日：2012-02-09
申请号：US13197755
申请日：2011-08-03
申请人： Koichi NONAKA , Satoru Nakanishi
发明人： Koichi NONAKA , Satoru Nakanishi
IPC分类号： G06F12/02
CPC分类号： G06F12/0866 , G06F2212/214 , Y02D10/13
摘要： A data processing device is provided enabling faster read access to data in an on-chip EEPROM with relative ease, without increasing the area occupied by the chip and its power consumption. The on-chip nonvolatile memory included in the data processing device is provided with a pre-read cache which latches all or part of data, once having been read to bit lines from an array of nonvolatile memory cells by selecting a row address, and a selecting circuit which selects a portion of the data latched by the pre-read cache by selecting a portion of columns. Control is performed to retain address information for data latched by the pre-read cache, inhibit latching new data into the pre-read cache for read access to data in the nonvolatile memory according to the same address as the retained address information, and cause the selecting circuit to select the data latched by the pre-read cache.
摘要翻译：提供了一种数据处理装置，其能够相对容易地更快地读取片内EEPROM中的数据，而不增加芯片占用的面积及其功耗。包括在数据处理装置中的片上非易失性存储器设置有预读高速缓冲存储器，其通过选择行地址从锁存非易失性存储器单元的阵列而将数据的全部或部分锁存到位线中，并且选择电路，其通过选择列的一部分来选择由预读高速缓存器锁存的数据的一部分。执行控制以保留由预读高速缓存锁存的数据的地址信息，根据与保留的地址信息相同的地址，禁止将新数据锁存到预读高速缓存中以对非易失性存储器中的数据进行读访问，并且使选择电路以选择由预读高速缓存锁存的数据。

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