专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5523965A Semiconductor memory device and method of manufacturing same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5523965A
公开(公告)日：1996-06-04
申请号：US361958
申请日：1994-12-22
申请人： Toru Kaga , Shoji Shukuri , Masahiro Moniwa , Dai Hisamoto
发明人： Toru Kaga , Shoji Shukuri , Masahiro Moniwa , Dai Hisamoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/786 , G11C11/24
CPC分类号： H01L27/10817
摘要： Short and long sides of each of capacitors held by a semiconductor memory device are respectively made shorter and longer so that the capacitors are laid over memory cell regions adjacent to each other. Thus, large capacity type capacitors whose circumferential length increases and total capacitor area greatly increases can be obtained without so increasing plane areas of the capacitors.
摘要翻译：由半导体存储器件保持的每个电容器的短边和长边分别制造得越来越短，使得电容器被放置在彼此相邻的存储器单元区域上。因此，在电容器的平面面积不增加的情况下，可以获得圆周长度增加和电容器面积大大增加的大容量型电容器。

2. 发明授权

US5115289A Semiconductor device and semiconductor memory device 失效
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US5115289A
公开(公告)日：1992-05-19
申请号：US742196
申请日：1991-08-05
申请人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
发明人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
IPC分类号： H01L21/336 , H01L21/339 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/108 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/786
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/10808 , H01L27/10826 , H01L27/10852 , H01L27/10873 , H01L27/10879 , H01L27/1108 , H01L29/1062 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/66954 , H01L29/78654 , H01L21/76278
摘要： A semiconductor device, such as an FET or a charge coupled device, is provided having a channel or a charge coupled portion formed in a thin semiconductor layer which is substantially perpendicular to the substrate. Necessary electrodes, such as the gate electrode, and necessary insulating layers can be added at the thin semiconductor layer, and can maintain the necessary amount of electric current by securing the height of the semiconductor layer. The structure has the advantage that it can have its plane size reduced. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.
摘要翻译：提供了诸如FET或电荷耦合器件的半导体器件，其具有形成在基本上垂直于衬底的薄半导体层中的沟道或电荷耦合部分。可以在薄的半导体层添加必要的电极，例如栅电极和必要的绝缘层，并且可以通过确保半导体层的高度来保持必要的电流量。该结构具有能够减小其平面尺寸的优点。此外，使用上述半导体器件的半导体存储器件适合于高集成度并且具有优异的电特性。

3. 发明授权

US5466621A Method of manufacturing a semiconductor device having silicon islands 失效
标题翻译：制造具有硅岛的半导体器件的方法
公开(公告)号：US5466621A
公开(公告)日：1995-11-14
申请号：US141027
申请日：1993-10-25
申请人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
发明人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
IPC分类号： H01L21/336 , H01L21/339 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/108 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/786 , H01L21/70 , H01L27/00
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/10808 , H01L27/10852 , H01L27/10873 , H01L27/1108 , H01L29/1062 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/66954 , H01L29/78654 , H01L21/76278 , Y10S148/014
摘要： A semiconductor device such as FET or charge coupled device, having a channel or a charge coupled portion provided in a thin semiconductor layer which is nearly perpendicular to the substrate and to which the necessary electrode such as the gate electrode and the necessary insulating layer are added can maintain the necessary amount of electric current by securing the height of the semiconductor layer and also can have its plane size reduced minutely. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.
摘要翻译：一种诸如FET或电荷耦合器件的半导体器件，其具有设置在薄半导体层中的沟道或电荷耦合部分，该半导体层几乎垂直于衬底并且添加诸如栅电极和必需绝缘层的必需电极可以通过确保半导体层的高度来保持必要的电流量，并且还可以使其平面尺寸微小地减小。此外，使用上述半导体器件的半导体存储器件适合于高集成度并且具有优异的电特性。

4. 发明授权

US5346834A Method for manufacturing a semiconductor device and a semiconductor memory device 失效
标题翻译：半导体装置及半导体存储装置的制造方法
公开(公告)号：US5346834A
公开(公告)日：1994-09-13
申请号：US845063
申请日：1992-03-03
申请人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
发明人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
IPC分类号： H01L21/336 , H01L21/339 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/108 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/786 , H01L21/265
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/10808 , H01L27/10852 , H01L27/10873 , H01L27/1108 , H01L29/1062 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/66954 , H01L29/78654 , H01L21/76278 , Y10S148/014
摘要： An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.
摘要翻译：提供了一种用于制造绝缘栅场效应晶体管的改进方法。作为第一步骤，在硅衬底上生长氧化硅膜，并且在其上沉积第一氮化硅膜。然后使用抗蚀剂图案作为掩模来蚀刻第一硅亚硝酸盐膜，氧化硅膜和硅衬底，以形成包括硅衬底的至少一部分的硅岛。然后在通过第二步骤暴露的硅衬底的表面上以及在硅岛的表面上生长第二氧化硅膜，并且在其上沉积第二硅亚硝酸盐膜。然后蚀刻第二硅亚硝酸盐膜以留下沉积在硅岛的侧壁上的第二硅亚硝酸盐膜的一部分。之后，通过硅衬底的表面的热氧化生长第三氧化硅膜，以将硅岛与硅衬底电隔离。接下来，在硅岛上形成栅电极，随后在硅岛中形成源极和漏极区域，采用栅电极作为掩模。

5. 发明申请

US20090152595A1 SEMICONDUCTOR DEVICES AND METHOD OF TESTING SAME 审中-公开
标题翻译：半导体器件及其测试方法
公开(公告)号：US20090152595A1
公开(公告)日：2009-06-18
申请号：US12066470
申请日：2006-09-08
申请人： Toru Kaga , Yoshihiko Naito , Masatoshi Tsuneoka , Kenji Terao , Nobuharu Noji , Ryo Tajima
发明人： Toru Kaga , Yoshihiko Naito , Masatoshi Tsuneoka , Kenji Terao , Nobuharu Noji , Ryo Tajima
IPC分类号： H01L23/522 , G01R31/302
CPC分类号： G01R31/307 , G01R31/2884 , G11C29/02 , G11C29/025
摘要： There are provided a semiconductor device having a pattern which allows electric failures to be sensitively detected at high speeds, and a method of testing the same. In one embodiment, the semiconductor device comprises a pair of row wires including a plurality of first wires arranged in a first layer at predetermined intervals in a row direction, where the first wires have ends connected to second wires arranged in a second layer at a predetermined intervals through vias, and the first wire and second wire are at the same potential. In the pair of row wires, a first wire positioned at a right end of one row wire is connected to a first conductor, and a first wire positioned at a left end in the other row wire is connected to a second conductor. By sequentially scanning the first conductor and second conductor using an electron beam, a change in the amount of emitted secondary electrons due to a difference in potential between these conductors is detected to detect electric anomalies.
摘要翻译：提供了具有能够高速灵敏地检测电故障的图案的半导体器件及其测试方法。在一个实施例中，半导体器件包括一对行导线，其包括以行方向以预定间隔布置在第一层中的多个第一布线，其中第一布线具有以预定的方式连接到布置在第二层中的第二布线通过通孔的间隔，并且第一线和第二线处于相同的电位。在一对行配线中，位于一列行的右端的第一配线与第一导体连接，位于另一行配线左端的第一配线与第二导体连接。通过使用电子束顺序扫描第一导体和第二导体，检测由于这些导体之间的电位差引起的发射二次电子量的变化，以检测电气异常。

6. 发明授权

US07385197B2 Electron beam apparatus and a device manufacturing method using the same apparatus 有权
标题翻译：电子束装置和使用该装置的装置制造方法
公开(公告)号：US07385197B2
公开(公告)日：2008-06-10
申请号：US11175390
申请日：2005-07-07
申请人： Mamoru Nakasuji , Nobuharu Noji , Tohru Satake , Takeshi Murakami , Hirosi Sobukawa , Toru Kaga , Masahiro Hatakayama
发明人： Mamoru Nakasuji , Nobuharu Noji , Tohru Satake , Takeshi Murakami , Hirosi Sobukawa , Toru Kaga , Masahiro Hatakayama
IPC分类号： G01N23/00 , G01K7/00
CPC分类号： G01N23/2251 , H01J37/244 , H01J37/28 , H01J2237/14 , H01J2237/1508 , H01J2237/1526 , H01J2237/2447 , H01J2237/24592
摘要： Disclosed is an electron beam apparatus, in which a plurality of electron beams is formed from electrons emitted from an electron gun 21 and used to irradiate a sample surface via an objective lens 28, said apparatus comprising: a beam separator 27 for separating a secondary electron beams emanating from respective scanned regions on the sample from the primary electron beams; a magnifying electron lens 31 for extending a beam space between adjacent beams in the separated plurality of secondary electron beams; a fiber optical plate 32 for converting the magnified plurality of secondary electron beams to optical signals by a scintillator and for transmitting the signals; a photoelectric conversion device 35 for converting the optical signal to an electric signal; an optical zoom lens 33 for focusing the optical signal from the scintillator into an image on the photoelectric conversion device; and a rotation mechanism 36 for rotating the photoelectric conversion device 35 around the optical axis.
摘要翻译：公开了一种电子束装置，其中从电子枪21发射的电子形成多个电子束，并用于经由物镜28照射样品表面，所述装置包括：用于分离二次电子的光束分离器27 来自一次电子束的样品上的各扫描区域发出的光束; 用于在分离的多个二次电子束中的相邻光束之间延伸光束空间的放大电子透镜31; 用于通过闪烁体将放大的多个二次电子束转换为光信号并用于发送信号的光纤光学板32; 用于将光信号转换为电信号的光电转换装置35; 用于将来自闪烁体的光信号聚焦到光电转换装置上的图像的光学变焦透镜33; 以及用于使光电转换装置35围绕光轴旋转的旋转机构36。

7. 发明授权

US06894334B2 Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US06894334B2
公开(公告)日：2005-05-17
申请号：US10376329
申请日：2003-03-03
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

8. 发明授权

US06548847B2 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM 失效
标题翻译：具有通过连接孔暴露的第一布线的半导体集成电路器件，连接孔中的过渡金属膜和铝导线之间的过渡金属膜以及铝导线和过渡金属膜之间的过渡金属氮化物膜
公开(公告)号：US06548847B2
公开(公告)日：2003-04-15
申请号：US09899921
申请日：2001-07-09
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： H01L2976
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

9. 发明授权

US5619055A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5619055A
公开(公告)日：1997-04-08
申请号：US429882
申请日：1995-04-27
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/76
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error. The overlapping relationship for effecting the large capacitor element across the source and gate of the respective load MISFETs is provided by an ion implanting scheme of a p-type impurity into the semiconductor strip. A separate mask for ion-implantation for the formation of the source region of the load MISFET is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region.
摘要翻译：公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET之上。存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由不同于导电膜的驱动MISFET组成的栅电极构成。在具有这种堆叠布置的存储器单元中，每个负载MISFET的源极区域和栅电极被图案化以具有彼此广泛重叠的关系，以形成电容器元件，使得与每个负载MISFET相关联的总体电容的增加存储单元存储节点被实现，从而减少软错误的发生。通过p型杂质离子注入到半导体条中的方式来提供跨越各个负载MISFET的源极和栅极的大电容器元件的重叠关系。添加用于形成负载MISFET的源极区域的离子注入的单独的掩模，然后以与源极区域具有广泛重叠的关系的方式添加其栅电极。

10. 发明授权

US5374576A Method of fabricating stacked capacitor cell memory devices 失效
标题翻译：叠层电容器单元存储器件的制造方法
公开(公告)号：US5374576A
公开(公告)日：1994-12-20
申请号：US72482
申请日：1993-06-03
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10808 , H01L27/10817 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式