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1. 发明授权

US5374576A Method of fabricating stacked capacitor cell memory devices 失效
标题翻译：叠层电容器单元存储器件的制造方法
公开(公告)号：US5374576A
公开(公告)日：1994-12-20
申请号：US72482
申请日：1993-06-03
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10808 , H01L27/10817 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

2. 发明授权

US06878586B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06878586B2
公开(公告)日：2005-04-12
申请号：US10458271
申请日：2003-06-11
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45 , H01L21/8242
CPC分类号： H01L27/10817 , H01L27/10808 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

3. 发明授权

US5591998A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5591998A
公开(公告)日：1997-01-07
申请号：US443106
申请日：1995-05-17
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45
CPC分类号： H01L27/10808 , H01L27/10817 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

4. 发明授权

US5583358A Semiconductor memory device having stacked capacitors 失效
标题翻译：具有层叠电容器的半导体存储器件
公开(公告)号：US5583358A
公开(公告)日：1996-12-10
申请号：US324352
申请日：1994-10-17
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45
CPC分类号： H01L27/10808 , H01L27/10817 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

5. 发明授权

US5140389A Semiconductor memory device having stacked capacitor cells 失效
标题翻译：具有层叠电容器单元的半导体存储器件
公开(公告)号：US5140389A
公开(公告)日：1992-08-18
申请号：US475148
申请日：1990-02-05
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储电容器要非常密集地布置的部分和足够大的电容以保持非常小的电池区域。由于存储电容器部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的电容减小，因此存储器阵列噪声减小。也可以设计电荷存储电容器部分，使得其一部分呈基本上垂直于衬底的壁的形式，以增加电容。

6. 发明授权

US5200635A Semiconductor device having a low-resistivity planar wiring structure 失效
标题翻译：具有低电阻率平面布线结构的半导体器件
公开(公告)号：US5200635A
公开(公告)日：1993-04-06
申请号：US686757
申请日：1991-04-17
申请人： Toru Kaga , Shinichiro Kimura , Katsutaka Kimura , Yoshinobu Nakagome , Digh Hisamoto , Yoshifumi Kawamoto , Eiji Takeda , Shimpei Iijima , Tokuo Kure , Takashi Nishida
发明人： Toru Kaga , Shinichiro Kimura , Katsutaka Kimura , Yoshinobu Nakagome , Digh Hisamoto , Yoshifumi Kawamoto , Eiji Takeda , Shimpei Iijima , Tokuo Kure , Takashi Nishida
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45
CPC分类号： H01L29/41775 , H01L27/10817 , H01L29/456 , H01L2924/0002
摘要： The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.
摘要翻译：本发明涉及具有低电阻率布线结构的半导体器件。直接形成在山谷和山谷结构上的布线导致薄的部分，并且在极端情况下是断开的部分。这增加了山丘和山谷结构上的布线电阻率，降低了连接的可靠性。在布线是存储器的数据线的情况下，随着有效长度的增加，数据线的电阻和寄生电容更大。上述问题已经通过包括至少两层导电膜的布线来解决，所述导电膜包括作为下层的第一导电膜和作为上层的第二导电膜，并且第一导电层具有调节或平坦化山丘的表面和底层材料中的山谷。

7. 发明授权

US5177576A Dynamic random access memory having trench capacitors and vertical transistors 失效
标题翻译：具有沟槽电容器和垂直晶体管的动态随机存取存储器
公开(公告)号：US5177576A
公开(公告)日：1993-01-05
申请号：US695984
申请日：1991-05-06
申请人： Shin'ichiro Kimura , Tokuo Kure , Toru Kaga , Digh Hisamoto , Eiji Takeda
发明人： Shin'ichiro Kimura , Tokuo Kure , Toru Kaga , Digh Hisamoto , Eiji Takeda
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10841
摘要： A vertical semiconductor memory device is provided which capable of miniaturization. More particularly, a memory cell is provided having a trench capacitor and a vertical transistor in a dynamic random access memory suitable for high density integration. An object of this arrangement is to provide a vertical memory cell capable of miniaturization for use in a ultra-high density integration DRAM of a Gbit class. This memory cell is characterized in that each memory cell is covered with an oxide film, an impurity area does not exist on the substrate side, an area in which a channel area is formed is a hollow cylindrical single crystal area, connection of impurity areas as source-drain areas and bit lines and the electrode of a capacitor is made by self-alignment and connection between a word line electrode and a gate electrode is also made by self-alignment.
摘要翻译：提供能够小型化的垂直半导体存储器件。更具体地说，在动态随机存取存储器中提供具有沟槽电容器和垂直晶体管的存储单元，其适用于高密度集成。这种布置的目的是提供一种能够小型化的垂直存储单元，用于Gbit级的超高密度集成DRAM。该存储单元的特征在于，每个存储单元被氧化物膜覆盖，基板侧不存在杂质区域，形成沟道区域的区域是中空圆柱形单晶区域，杂质区域的连接为源极 - 漏极区域和位线，并且电容器的电极通过自对准而形成，并且字线电极和栅电极之间的连接也通过自对准来进行。

8. 发明授权

US5296729A Semiconductor memory device having static random access memory 失效
标题翻译：具有静态随机存取存储器的半导体存储器件
公开(公告)号：US5296729A
公开(公告)日：1994-03-22
申请号：US782623
申请日：1991-10-25
申请人： Toshiaki Yamanaka , Norio Hasegawa , Toshihiko Tanaka , Takashi Hashimoto , Koichiro Ishibashi , Naotaka Hashimoto , Akihiro Shimizu , Yasuhiro Sugawara , Tokuo Kure , Shimpei Iijima , Takashi Nishida , Eiji Takeda
发明人： Toshiaki Yamanaka , Norio Hasegawa , Toshihiko Tanaka , Takashi Hashimoto , Koichiro Ishibashi , Naotaka Hashimoto , Akihiro Shimizu , Yasuhiro Sugawara , Tokuo Kure , Shimpei Iijima , Takashi Nishida , Eiji Takeda
IPC分类号： G03F1/29 , G03F1/30 , G03F1/68 , H01L21/027 , H01L21/8244 , H01L27/11 , H01L27/02 , H01L29/00 , H01L29/78
CPC分类号： H01L27/1108 , Y10S257/903
摘要： There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.
摘要翻译：提供了一种能够通过扩大连接到存储单元的标准电位电源的单元中的电极的有效面积来减小电极电阻的技术。还提供了一种能够通过减小用于标准电位电极的电极中的电极与相邻的其它电极之间分离所需的面积来减小存储单元面积的技术。提供了第一导电类型的两个传输MOS晶体管和两个驱动器MOS晶体管。用于将驱动器MOS晶体管的源极电位固定为标准电位的导电层设置在传输和驱动器MOS晶体管之上，以完全覆盖存储器单元。通过使用具有设置在相同透射部分内的光学透明基板的光掩模进行分离，其具有多个所谓的移相器区域的图案，用于反转透射相位的相位。

9. 发明授权

US5357464A Semiconductor memory having writing and reading transistors, method of fabrication thereof, and method of use thereof 失效
标题翻译：具有写入和读取晶体管的半导体存储器，其制造方法及其使用方法
公开(公告)号：US5357464A
公开(公告)日：1994-10-18
申请号：US22937
申请日：1993-02-26
申请人： Shuji Shukuri , Toru Koga , Shinichiro Kimura , Digh Hisamoto , Kazuhiko Sagara , Tokuo Kure , Eiji Takeda
发明人： Shuji Shukuri , Toru Koga , Shinichiro Kimura , Digh Hisamoto , Kazuhiko Sagara , Tokuo Kure , Eiji Takeda
IPC分类号： H01L27/10 , G11C11/401 , G11C11/402 , H01L21/8242 , H01L27/108 , G11C11/40
CPC分类号： G11C11/401 , H01L27/108
摘要： Disclosed is a semiconductor memory having a self-amplifying cell structure, using (1) a writing transistor and (2) a reading transistor with a floating gate as a charge storage node for each memory cell, and a method of fabricating the memory cell. The writing transistor and reading transistor are of opposite conductivity type to each other; for example, the writing transistor uses a P-channel MOS transistor and the reading transistor (having the floating gate) uses an N-channel MOS transistor. The floating gate of the reading transistor is connected to a single bit line through a source-drain path of the writing transistor, the source-drain path of the reading transistor is connected between the single bit line and a predetermined potential, and the gate electrodes of the writing and reading transistors are connected to a single word line. At least the reading transistor can be formed in a trench, and the word line can be formed overlying the writing transistor and the reading transistor in the trench. Also disclosed is a method of operating the memory cell, wherein the voltage applied to the word line, in a standby condition, is intermediate to the voltage applied to the word line during the writing operation and during the reading operation.
摘要翻译：公开了具有自放大单元结构的半导体存储器，其使用（1）写入晶体管和（2）具有浮置栅极的读取晶体管作为每个存储单元的电荷存储节点，以及制造该存储单元的方法。写入晶体管和读取晶体管彼此具有相反的导电类型; 例如，写入晶体管使用P沟道MOS晶体管，并且读取晶体管（具有浮置栅极）使用N沟道MOS晶体管。读取晶体管的浮置栅极通过写入晶体管的源极 - 漏极连接到单个位线，读取晶体管的源极 - 漏极连接在单个位线和预定电位之间，并且栅电极的写和读晶体管连接到单个字线。至少读取晶体管可以形成在沟槽中，并且字线可以形成在沟槽中的写入晶体管和读取晶体管的上方。还公开了一种操作存储单元的方法，其中在备用状态下施加到字线的电压在写入操作期间和在读取操作期间施加到字线的电压的中间。

10. 发明授权

US5346834A Method for manufacturing a semiconductor device and a semiconductor memory device 失效
标题翻译：半导体装置及半导体存储装置的制造方法
公开(公告)号：US5346834A
公开(公告)日：1994-09-13
申请号：US845063
申请日：1992-03-03
申请人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
发明人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
IPC分类号： H01L21/336 , H01L21/339 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/108 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/786 , H01L21/265
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/10808 , H01L27/10852 , H01L27/10873 , H01L27/1108 , H01L29/1062 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/66954 , H01L29/78654 , H01L21/76278 , Y10S148/014
摘要： An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.
摘要翻译：提供了一种用于制造绝缘栅场效应晶体管的改进方法。作为第一步骤，在硅衬底上生长氧化硅膜，并且在其上沉积第一氮化硅膜。然后使用抗蚀剂图案作为掩模来蚀刻第一硅亚硝酸盐膜，氧化硅膜和硅衬底，以形成包括硅衬底的至少一部分的硅岛。然后在通过第二步骤暴露的硅衬底的表面上以及在硅岛的表面上生长第二氧化硅膜，并且在其上沉积第二硅亚硝酸盐膜。然后蚀刻第二硅亚硝酸盐膜以留下沉积在硅岛的侧壁上的第二硅亚硝酸盐膜的一部分。之后，通过硅衬底的表面的热氧化生长第三氧化硅膜，以将硅岛与硅衬底电隔离。接下来，在硅岛上形成栅电极，随后在硅岛中形成源极和漏极区域，采用栅电极作为掩模。

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