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1. 发明授权

US5374576A Method of fabricating stacked capacitor cell memory devices 失效
标题翻译：叠层电容器单元存储器件的制造方法
公开(公告)号：US5374576A
公开(公告)日：1994-12-20
申请号：US72482
申请日：1993-06-03
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10808 , H01L27/10817 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

2. 发明授权

US5591998A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5591998A
公开(公告)日：1997-01-07
申请号：US443106
申请日：1995-05-17
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45
CPC分类号： H01L27/10808 , H01L27/10817 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

3. 发明授权

US5583358A Semiconductor memory device having stacked capacitors 失效
标题翻译：具有层叠电容器的半导体存储器件
公开(公告)号：US5583358A
公开(公告)日：1996-12-10
申请号：US324352
申请日：1994-10-17
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45
CPC分类号： H01L27/10808 , H01L27/10817 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

4. 发明授权

US5140389A Semiconductor memory device having stacked capacitor cells 失效
标题翻译：具有层叠电容器单元的半导体存储器件
公开(公告)号：US5140389A
公开(公告)日：1992-08-18
申请号：US475148
申请日：1990-02-05
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储电容器要非常密集地布置的部分和足够大的电容以保持非常小的电池区域。由于存储电容器部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的电容减小，因此存储器阵列噪声减小。也可以设计电荷存储电容器部分，使得其一部分呈基本上垂直于衬底的壁的形式，以增加电容。

5. 发明授权

US06878586B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06878586B2
公开(公告)日：2005-04-12
申请号：US10458271
申请日：2003-06-11
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45 , H01L21/8242
CPC分类号： H01L27/10817 , H01L27/10808 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

6. 发明授权

US5200635A Semiconductor device having a low-resistivity planar wiring structure 失效
标题翻译：具有低电阻率平面布线结构的半导体器件
公开(公告)号：US5200635A
公开(公告)日：1993-04-06
申请号：US686757
申请日：1991-04-17
申请人： Toru Kaga , Shinichiro Kimura , Katsutaka Kimura , Yoshinobu Nakagome , Digh Hisamoto , Yoshifumi Kawamoto , Eiji Takeda , Shimpei Iijima , Tokuo Kure , Takashi Nishida
发明人： Toru Kaga , Shinichiro Kimura , Katsutaka Kimura , Yoshinobu Nakagome , Digh Hisamoto , Yoshifumi Kawamoto , Eiji Takeda , Shimpei Iijima , Tokuo Kure , Takashi Nishida
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45
CPC分类号： H01L29/41775 , H01L27/10817 , H01L29/456 , H01L2924/0002
摘要： The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.
摘要翻译：本发明涉及具有低电阻率布线结构的半导体器件。直接形成在山谷和山谷结构上的布线导致薄的部分，并且在极端情况下是断开的部分。这增加了山丘和山谷结构上的布线电阻率，降低了连接的可靠性。在布线是存储器的数据线的情况下，随着有效长度的增加，数据线的电阻和寄生电容更大。上述问题已经通过包括至少两层导电膜的布线来解决，所述导电膜包括作为下层的第一导电膜和作为上层的第二导电膜，并且第一导电层具有调节或平坦化山丘的表面和底层材料中的山谷。

7. 发明授权

US4970564A Semiconductor memory device having stacked capacitor cells 失效
标题翻译：具有层叠电容器单元的半导体存储器件
公开(公告)号：US4970564A
公开(公告)日：1990-11-13
申请号：US287881
申请日：1988-12-21
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10808
摘要： A semiconductor memory device having STC cells wherein major portions of active regions consisting of channel-forming portions are tilted at an angle of 45.degree. with respect to the word lines and the bit lines that meet at right angles with each other, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas. In the semiconductor memory device, furthermore, the storage capacity portions are formed even on the bit lines. Therefore, the bit lines are shielded, the capacitance between the bit lines decreases, and the memory array noise decreases.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45°的角度倾斜，使得存储容量部分布置得非常密集和足够大的容量保持非常小的单元格区域。此外，在半导体存储器件中，即使在位线上形成存储容量部分。因此，位线被屏蔽，位线之间的电容减小，并且存储器阵列噪声降低。

8. 发明授权

US4873203A Method for formation of insulation film on silicon buried in trench 失效
标题翻译：在埋在沟槽中的硅上形成绝缘膜的方法
公开(公告)号：US4873203A
公开(公告)日：1989-10-10
申请号：US221351
申请日：1988-07-19
申请人： Toru Kaga , Shinichiro Kimura , Tokuo Kure , Yoshifumi Kawamoto , Hideo Sunami
发明人： Toru Kaga , Shinichiro Kimura , Tokuo Kure , Yoshifumi Kawamoto , Hideo Sunami
IPC分类号： H01L27/04 , H01L21/316 , H01L21/32 , H01L21/334 , H01L21/763 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L29/66181 , H01L21/32 , H01L21/763
摘要： An insulation film on silicon buried in a trench is prepared by forming a field oxide film by using a first Si.sub.3 N.sub.4 mask formed on a silicon substrate, forming a second Si.sub.3 N.sub.4 mask for formation of a trench, forming a trench in the silicon substrate by using the second Si.sub.3 N.sub.4 mask, burying polycrystalline silicon in the trench, removing the second Si.sub.3 N.sub.4 mask while leaving the first Si.sub.3 N.sub.4 mask and oxidizing the surface of the polycrystalline silicon buried in the trench by thermal oxidation. The so-formed insulation film on silicon buried in the trench has a uniform thickness and a high dielectric strength. The surface of the substrate at a part where an active element will be formed in the future is not oxidized.
摘要翻译：通过使用在硅衬底上形成的第一Si 3 N 4掩模形成场氧化膜，形成用于形成沟槽的第二Si 3 N 4掩模，通过使用硅衬底形成硅衬底中的沟槽来制备掩埋在沟槽中的硅上的绝缘膜第二Si 3 N 4掩模，在沟槽中埋入多晶硅，除去第二Si 3 N 4掩模，同时留下第一Si 3 N 4掩模，并通过热氧化氧化掩埋在沟槽中的多晶硅的表面。埋在沟槽中的硅上如此形成的绝缘膜具有均匀的厚度和高介电强度。在将来将形成有源元件的部分处的基板的表面不被氧化。

9. 发明授权

US5357464A Semiconductor memory having writing and reading transistors, method of fabrication thereof, and method of use thereof 失效
标题翻译：具有写入和读取晶体管的半导体存储器，其制造方法及其使用方法
公开(公告)号：US5357464A
公开(公告)日：1994-10-18
申请号：US22937
申请日：1993-02-26
申请人： Shuji Shukuri , Toru Koga , Shinichiro Kimura , Digh Hisamoto , Kazuhiko Sagara , Tokuo Kure , Eiji Takeda
发明人： Shuji Shukuri , Toru Koga , Shinichiro Kimura , Digh Hisamoto , Kazuhiko Sagara , Tokuo Kure , Eiji Takeda
IPC分类号： H01L27/10 , G11C11/401 , G11C11/402 , H01L21/8242 , H01L27/108 , G11C11/40
CPC分类号： G11C11/401 , H01L27/108
摘要： Disclosed is a semiconductor memory having a self-amplifying cell structure, using (1) a writing transistor and (2) a reading transistor with a floating gate as a charge storage node for each memory cell, and a method of fabricating the memory cell. The writing transistor and reading transistor are of opposite conductivity type to each other; for example, the writing transistor uses a P-channel MOS transistor and the reading transistor (having the floating gate) uses an N-channel MOS transistor. The floating gate of the reading transistor is connected to a single bit line through a source-drain path of the writing transistor, the source-drain path of the reading transistor is connected between the single bit line and a predetermined potential, and the gate electrodes of the writing and reading transistors are connected to a single word line. At least the reading transistor can be formed in a trench, and the word line can be formed overlying the writing transistor and the reading transistor in the trench. Also disclosed is a method of operating the memory cell, wherein the voltage applied to the word line, in a standby condition, is intermediate to the voltage applied to the word line during the writing operation and during the reading operation.
摘要翻译：公开了具有自放大单元结构的半导体存储器，其使用（1）写入晶体管和（2）具有浮置栅极的读取晶体管作为每个存储单元的电荷存储节点，以及制造该存储单元的方法。写入晶体管和读取晶体管彼此具有相反的导电类型; 例如，写入晶体管使用P沟道MOS晶体管，并且读取晶体管（具有浮置栅极）使用N沟道MOS晶体管。读取晶体管的浮置栅极通过写入晶体管的源极 - 漏极连接到单个位线，读取晶体管的源极 - 漏极连接在单个位线和预定电位之间，并且栅电极的写和读晶体管连接到单个字线。至少读取晶体管可以形成在沟槽中，并且字线可以形成在沟槽中的写入晶体管和读取晶体管的上方。还公开了一种操作存储单元的方法，其中在备用状态下施加到字线的电压在写入操作期间和在读取操作期间施加到字线的电压的中间。

10. 发明授权

US5012310A Semiconductor memory having stacked capacitor 失效
标题翻译：半导体存储器具有层叠电容
公开(公告)号：US5012310A
公开(公告)日：1991-04-30
申请号：US566315
申请日：1990-08-13
申请人： Shinichiro Kimura , Yoshifumi Kawamoto , Toru Kaga , Hideo Sunami
发明人： Shinichiro Kimura , Yoshifumi Kawamoto , Toru Kaga , Hideo Sunami
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10808
摘要： A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.
摘要翻译：公开了一种实现高集成度和高可靠性的兆比特动态随机存取存储器。消除了对制造堆叠式电容器存储单元进行的光掩模对准的允许的需要。每个存储单元的平板电极通过绝缘膜与存储器阵列中的对应数据线隔离，该绝缘膜自行设置在平板电极周围。

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