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    • 1. 发明申请
    • Multilevel parallel CRC generation and checking circuit
    • 多级并行CRC生成和检查电路
    • US20050172205A1
    • 2005-08-04
    • US10771823
    • 2004-02-03
    • Ming-i LinBrian ConnollyTodd LeonardGregory MannJonathan Raymond
    • Ming-i LinBrian ConnollyTodd LeonardGregory MannJonathan Raymond
    • G06K5/04G11B5/00G11B20/20H03M13/00H03M13/09
    • H03M13/091
    • A CRC generator/checker for generating CRC results, comprising: a set of CRC circuits connected in series, each CRC circuit responsive to a different control signal generated by a control logic, each CRC circuit having a seed input adapted to receive a seed, a data input adapted to receive and process a different set of M-bits of a data unit and a result output adapted to generate a result, the result output of a previous CRC circuit connected to the seed input of an immediately subsequent CRC circuit, the seed input of a first CRC circuit connected to an output of a remainder register, an input of the remainder register connected to an output of a multiplexer, the result outputs of the multiplicity of CRC circuits connected to different inputs of the multiplexer, the multiplexer responsive to a select signal generated by the control logic.
    • 一种用于生成CRC结果的CRC发生器/检验器,包括:串联连接的一组CRC电路,每个CRC电路响应于由控制逻辑产生的不同控制信号,每个CRC电路具有适于接收种子的种子输入, 数据输入,适于接收和处理数据单元的不同的M位组,以及适于产生结果的结果输出,连接到紧接着的CRC电路的种子输入的先前CRC电路的结果输出,种子 连接到余数寄存器的输出的第一CRC电路的输入,连接到多路复用器的输出的剩余寄存器的输入,结果连接到多路复用器的不同输入的多个CRC电路的输出,多路复用器响应于 由控制逻辑产生的选择信号。
    • 2. 发明申请
    • Scalable cyclic redundancy check circuit
    • 可扩展循环冗余校验电路
    • US20050138523A1
    • 2005-06-23
    • US10729277
    • 2003-12-04
    • Todd LeonardGregory Mann
    • Todd LeonardGregory Mann
    • H03M13/09G11B5/00G06K5/04G11B20/20H03M13/00
    • H03M13/091
    • A CRC circuit, CRC method, and method of designing a CRC circuit, the CRC circuit, including: a packet data slice latch having outputs; a multiple level XOR subtree, each level including one or more XOR subtrees, each output of the packet data slice latch coupled to an input of the multiple level XOR subtree, each lower level XOR subtree coupled to a higher level XOR subtree through an intervening latch level; a remainder XOR subtree; a combinational XOR subtree, the outputs of the remainder XOR subtree and the outputs of the multiple level XOR subtree coupled to the inputs of the combinational XOR subtree; and a current CRC result latch, the output of the combinational XOR subtree coupled to the inputs of the current CRC result latch and the outputs of the M-bit current CRC result latch coupled to the inputs of the remainder XOR subtree.
    • CRC电路,CRC方法和CRC电路的设计方法,CRC电路包括:具有输出的分组数据片锁存器; 多级XOR子树,每个级别包括一个或多个异或子树,分组数据片锁存器的每个输出耦合到多级XOR子树的输入,每个下级XOR子树通过中间锁存器耦合到较高级XOR子树 水平; 余数XOR子树; 组合XOR子树,余数XOR子树的输出和耦合到组合XOR子树的输入的多级XOR子树的输出; 和当前CRC结果锁存器,耦合到当前CRC结果锁存器的输入的组合XOR子树的输出和耦合到余数XOR子树的输入的M位当前CRC结果锁存器的输出。
    • 3. 发明申请
    • CYCLIC REDUNDANCY CHECK GENERATION CIRCUIT
    • 循环冗余检查生成电路
    • US20050268209A1
    • 2005-12-01
    • US10709794
    • 2004-05-28
    • Gregory Mann
    • Gregory Mann
    • H03M13/00H03M13/09
    • H03M13/091H03M13/6572
    • A circuit, a method, and a method of designing the circuit, the circuit including: multiple W-bit packet data slice latches; a data partition comprising multiple data XOR subtree levels and having data latches between the data XOR subtree levels; a remainder partition comprising multiple remainder XOR subtree levels and having remainder latches between the remainder XOR subtree levels; a combinatorial XOR tree, outputs of the remainder partition and outputs of the data partition connected to inputs of the combinatorial XOR tree; and a remainder latch, combinatorial XOR tree connected to the remainder latch and the outputs of the remainder latch connected to the remainder partition.
    • 一种设计电路的电路,方法和方法,所述电路包括:多个W位分组数据片锁存器; 数据分区,包括多个数据XOR子树级别,并且在数据XOR子树级之间具有数据锁存器; 剩余分区包括多个余数XOR子树级别,并且在余数XOR子树级别之间具有余数锁存器; 组合XOR树,连续到组合XOR树的输入的数据分区的剩余分区和输出的输出; 以及连接到剩余锁存器的剩余锁存组合XOR树,并且剩余锁存器的输出连接到其余分区。
    • 7. 发明申请
    • METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-QUALIFIED EXPOSURE MASKS FOR SELECTED BLOCKS OF CIRCUITRY
    • 使用预先制作的集成电路的方法和用于选择的电路块的预先准许的接触掩模
    • US20070245290A1
    • 2007-10-18
    • US11279666
    • 2006-04-13
    • Serafino BuetiKenneth GoodnowGregory MannJason Norman
    • Serafino BuetiKenneth GoodnowGregory MannJason Norman
    • G06F17/50G03F1/00
    • G03F1/84
    • Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to pattern a chip design onto a silicon wafer, where the chip design is made up of two or more interconnected blocks of circuitry. Consequently, for a given integrated circuit design, pre-made/pre-qualified mask(s) can be selected from the library to pattern one, some or all blocks of circuitry for the design. Optionally, additional masks can be specially made and qualified to pattern other block(s) of circuitry (e.g., application specific logic) within the design. The blocks of circuitry patterned in this manner can be electrically connected via generic or customized interfaces in order to complete the chip design.
    • 公开了一种制造方法的实施例,其建立用于图案化满足已确定的性能和时序要求的不同电路块的预制和预先限定的掩模库。 该方法的实施例使用多个掩模的步进曝光,包括从该库选择的至少一个掩模,以将芯片设计图案化到硅晶片上,其中芯片设计由两个或更多个互连的电路块组成。 因此,对于给定的集成电路设计,可以从库中选择预制/预先限定的掩模,以对设计的一个,一些或所有电路块进行图案化。 可选地,附加掩模可以被特别地制造并且被限定以在设计中对其他电路块(例如,应用专用逻辑)进行图案化。 以这种方式图案化的电路块可通过通用或定制界面电连接,以完成芯片设计。
    • 8. 发明申请
    • Methods, systems, and computer program products for providing dynamic data of positional localization of target implants
    • 用于提供目标植入物位置定位的动态数据的方法,系统和计算机程序产品
    • US20070161884A1
    • 2007-07-12
    • US10551366
    • 2004-03-29
    • Robert BlackGregory MannSteven Widener
    • Robert BlackGregory MannSteven Widener
    • A61B5/05
    • A61N5/1048A61B5/0008A61B5/0031A61B5/06A61B5/062A61B34/20A61B90/37A61B90/98A61B2017/00022A61B2017/00411A61B2034/107A61B2034/2051A61B2034/2072A61B2090/397A61B2090/3975A61N2005/1051
    • Systems for locating implanted in vivo sensors systems adapted for use with an external beam radiation therapy delivery source include: (a) an external solenoid member; (b) an articulated arm opertively associated with the external solenoid member, wherein, in operation, the articulated arm is configured to translate the solenoid; (c) a controller configured to direct the movement of the articulated arm, the controller being in communication with the power source configured to power the external solenoid; (d) at least one implantable sensors unit, wherein the at least one implantable sensor unit is configured to sense at least one predetermined parameter of interest in vivo, and wherein the at least one implantable sensor unit comprises a solenoid, and wherein, in operation, the sensor unit solenoid corporates with the external solenoid to generate a magnetic coupling signal having a signal strength that varies based on the possession of the external solenoid member relative to the implanted sensors unit; (e) a computer module in communication with the controller comprising computer programmed code that evaluates the coupling signal strength in relation to the position of the external solenoid and determines the position of the at least one sensor unit; and (f) an external reader configured to wirelessly communicate with the at least one implantable sensor unit to obtain data associated with the at least one predetermined parameter of interest.
    • 用于定位适于与外部束放射治疗递送源一起使用的植入体内传感器系统的系统包括:(a)外部螺线管部件; (b)与所述外部螺线管构件动作关联的铰接臂,其中,在操作中,所述铰接臂构造成平移所述螺线管; (c)控制器,其被配置为引导所述铰接臂的移动,所述控制器与被配置为对所述外部螺线管供电的所述电源连通; (d)至少一个可植入传感器单元,其中所述至少一个可植入传感器单元被配置为在体内感测至少一个预期的感兴趣参数,并且其中所述至少一个可植入传感器单元包括螺线管,并且其中,在操作中 传感器单元螺线管与外部螺线管合并产生具有基于外部螺线管部件相对于植入传感器单元的占有而变化的信号强度的磁耦合信号; (e)与所述控制器通信的计算机模块,包括计算机编程代码,所述计算机程序代码评估与所述外部螺线管的位置相关联的耦合信号强度并确定所述至少一个传感器单元的位置; 和(f)外部读取器,其被配置为与所述至少一个可植入传感器单元无线通信,以获得与所述至少一个预定的感兴趣参数相关联的数据。