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1. 发明申请

US20060041705A1 SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DEVICES IN SYSTEM ON CHIP ARCHITECTURES 审中-公开
标题翻译：芯片结构体系中共享外围核心器件之间的仲裁系统和方法
公开(公告)号：US20060041705A1
公开(公告)日：2006-02-23
申请号：US10711084
申请日：2004-08-20
申请人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman , Scott Vento
发明人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman , Scott Vento
IPC分类号： G06F13/36
CPC分类号： G06F13/4031 , G06F2213/0038
摘要： A system for implementing arbitration between one or more shared peripheral core devices in system on chip (SOC) integrated circuit architecture includes a first microprocessor in communication with a first system bus, and a second microprocessor in communication with a second system bus. At least one peripheral core device is accessible by both the first microprocessor and said second microprocessor, and an arbitration unit is in communication with the first system bus and the second system bus. The arbitration unit is configured to control communication between the at least one peripheral core device and the first and second microprocessors.
摘要翻译：一种用于在系统级芯片（SOC）集成电路架构中的一个或多个共享外围核心装置之间实现仲裁的系统包括与第一系统总线通信的第一微处理器和与第二系统总线通信的第二微处理器。至少一个外围核心设备可由第一微处理器和所述第二微处理器访问，并且仲裁单元与第一系统总线和第二系统总线通信。仲裁单元被配置为控制至少一个外围核心设备与第一和第二微处理器之间的通信。

2. 发明申请

US20070266349A1 DIRECTED RANDOM VERIFICATION 审中-公开
标题翻译：指导随机验证
公开(公告)号：US20070266349A1
公开(公告)日：2007-11-15
申请号：US11382371
申请日：2006-05-09
申请人： Jesse Craig , Scott Vento , Stanley Stanski , Andrew Wienick
发明人： Jesse Craig , Scott Vento , Stanley Stanski , Andrew Wienick
IPC分类号： G06F17/50 , G06F11/00 , G01R31/28
CPC分类号： G01R31/318385 , G06F11/263
摘要： A directed random verification system and method analyzes a pair of generated test cases, from a pool of generated test cases which are capable of testing at least a portion of an untested coverage event, and finds a logical, deterministic crossover point between at least two test cases. Once a pair of test cases with at least one crossover point has been identified the method crosses a portion of the random number trace up to the crossover point with a portion of the second random number trace, which continues from the crossover point. The result is a new random number trace that is a combination of a portion of one test and a portion of another test. The new random number trace is sent to the stimulus generator as the new random number input.
摘要翻译：定向随机验证系统和方法从生成的测试用例池中分析一对生成的测试用例，该测试用例能够测试至少一部分未经测试的覆盖事件，并在至少两个测试之间找到逻辑的确定性交叉点案件一旦已经确定了具有至少一个交叉点的一对测试用例，该方法将随机数曲线的一部分与第二随机数迹线的一部分交叉到交叉点，该部分从交叉点继续。结果是一个新的随机数迹线，它是一个测试的一部分和另一个测试的一部分的组合。新的随机数字轨迹作为新的随机数输入发送到刺激发生器。

3. 发明申请

US20070005290A1 METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE THROUGH DETERMINISTIC PATH DELAYS 失效
标题翻译：通过确定性延迟监测集成电路温度的方法和装置
公开(公告)号：US20070005290A1
公开(公告)日：2007-01-04
申请号：US11160601
申请日：2005-06-30
申请人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Jason Norman , Stanley Stanski , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Jason Norman , Stanley Stanski , Scott Vento
IPC分类号： G01K1/00
CPC分类号： G01K3/14 , G01K3/10
摘要： An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.
摘要翻译：用于监测集成电路器件的温度的装置包括形成在集成电路器件上的导电布线图形，延伸到待监视器件的区域中。确定性信号源被配置为沿着导电布线图形生成确定性信号，其中从沿着图案的选定位置抽头的一个或多个返回路径。温度变化确定电路耦合到一个或多个返回路径以及从确定性信号源获取的参考信号。该电路被配置为确定参考信号和穿过布线图案的至少一部分和相应的一个返回路径的延迟信号之间的延迟。

4. 发明申请

US20060242524A1 SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION 失效
标题翻译：系统与片上互连验证的系统和方法
公开(公告)号：US20060242524A1
公开(公告)日：2006-10-26
申请号：US10906388
申请日：2005-02-17
申请人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/261 , G01R31/31717 , G01R31/318513 , G06F11/2236 , G06F17/5022
摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.
摘要翻译：一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较线性反馈移位寄存器和报告错误比较。

5. 发明申请

US20060095905A1 METHOD AND APPARATUS FOR SERVICING THREADS WITHIN A MULTI-PROCESSOR SYSTEM 审中-公开
标题翻译：用于在多处理器系统中维护螺纹的方法和装置
公开(公告)号：US20060095905A1
公开(公告)日：2006-05-04
申请号：US10904259
申请日：2004-11-01
申请人： Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
发明人： Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： A method for servicing threads within a multi-processor system is disclosed. In response to an input/output (I/O) request to a peripheral by a thread, a latency time is assigned to the thread such that the thread will not be interrogated until the latency time has lapsed. After the latency time is lapsed, a determination is made as to whether or not the I/O request has been responded. If the I/O request has not been responded after the latency time is lapsed, the latency time is assigned to the thread again. Otherwise, if the I/O request has been responded after the latency time is lapsed, the latency time is updated with an actual response time. The actual response time is from a time when the I/O request was made to a time when the I/O request was actually responded.
摘要翻译：公开了一种用于在多处理器系统内维护线程的方法。响应于线程对外设的输入/输出（I / O）请求，延迟时间被分配给线程，使得在延迟时间过去之前线程将不被询问。在延迟时间过去之后，确定I / O请求是否已被响应。如果延迟时间过后I / O请求未被响应，则延迟时间将再次分配给该线程。否则，如果在延迟时间过后已经响应了I / O请求，则延迟时间将以实际响应时间更新。实际的响应时间是从I / O请求到实际响应I / O请求时的时间。

6. 发明申请

US20060038444A1 COMMUNICATION SYSTEMS AND METHODS USING MICROELECTRONICS POWER DISTRIBUTION NETWORK 失效
标题翻译：通信系统和使用微电子功率分配网络的方法
公开(公告)号：US20060038444A1
公开(公告)日：2006-02-23
申请号：US10711082
申请日：2004-08-20
申请人： Serafino Bueti , Adam Courchesne , Kai Feng , Kenneth Goodnow , Gregory Mann , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kai Feng , Kenneth Goodnow , Gregory Mann , Scott Vento
IPC分类号： H04B3/54 , G05B11/01
CPC分类号： H04B3/54 , H04B2203/5416
摘要： A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to receive the communication signal from the power distribution network. A method is also provided for transmitting a communication signal via a power distribution network of a microelectronics chip.
摘要翻译：一种通信系统，其包括具有配电网络的微电子芯片; 发射机，可操作地配置为产生通信信号并将所述通信信号提供给所述配电网络; 以及可操作地配置为从所述配电网接收所述通信信号的接收器。还提供了一种通过微电子芯片的配电网传送通信信号的方法。

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